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AC '97 SoundMAX(R) Codec AD1985
AC '97 2.3 COMPLIANT FEATURES
6 DAC channels for 5.1 surround Greater than 90 dB dynamic range 20-bit resolution on all DACs S/PDIF Output Integrated stereo headphone amplifiers Variable rate audio Double rate audio (fS = 96 kHz) Line-level mono phone input High quality CD mixer input Selectable MIC input with preamp AUX and line in stereo inputs External amplifier power down (EAPD) Power management modes Jack sensing and peripheral enumeration/identification 48-lead LQFP package
ENHANCED FEATURES
Integrated parametric equalizer (EQ) Stereo microphone with preamplifiers Integrated PLL for system clocking Variable sample rate 7 kHz to 96 kHz 7 kHz to 48 kHz in 1 Hz increments 96 kHz for double rate audio Advanced jack sense with auto topology switching Software enabled VREFOUT for microphones and external power amp Software enabled outputs for jack sharing Auto down-mix and channel spreading Microphone to mono output Stereo microphone analog passthrough to outputs Built-in stereo microphone and Center/LFE pin sharing Selectable Center/LFE tip/ring swapping to support various speaker products
FUNCTIONAL BLOCK DIAGRAM
VREFOUT
OMS
VREF Z G VOLTAGE REFERENCE CODEC CORE PCM L/R ADC RATE 16-BIT - ADC 16-BIT - ADC PCM C/LFE DAC RATE
XTL_OUT XTL_IN SPDIF_OUT
MIC1 MIC2 PHONE_IN CD_L CD_GND CD_R AUX_L AUX_R LINE_IN_L LINE_IN_R
AD1985
G
2CMIC MS
G
SPDIF TX
OMS
PLL ADC SLOT LOGIC
AC '97 INTERFACE V2.3
RECORD SELECTOR
ID0
CD DIFF AMP
G G
M M
ID1
RESET
LFE_OUT
MZ
A
SPRD
M
GA
20-BIT - DAC 20-BIT - DAC
CSWP
DAC SLOT LOGIC
SYNC
CENTER_OUT
MZ
A
LOSEL
SPRD
M GA MMM GA M GA M GA M GA M GA M GA M GA M M A GA MMM
GA
CSWP
BITCLK
LINE_OUT_L
MZ
A
EQ COEF STORAGE
MONO_OUT
M
A
MIX
PC BEEP GENERATOR PCM FRONT DAC RATE 20-BIT - DAC 20-BIT - DAC 20-BIT - DAC 20-BIT - DAC PCM SURR DAC RATE
BYPASS
SDATA_OUT
LOSEL
EQ
SDATA_IN
LINE_OUT_R
MZ
A
BYPASS
HPSEL

M M
M M M
GA GA GA GA
SURR_OUT_L/ HP_OUT_L SURR_OUT_R/ HP_OUT_R
HP M
A
EQ
AC '97 CONTROL REGISTERS ANALOG MIXING CONTROL JACK SENSE
HP M
A
HPSEL
EAPD JS0 JS1 JS2 JS3
Figure 1. Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
03610-A-001
G = GAIN A = ATTENUATION M = MUTE Z = HIGH Z
M
EAPD
AD1985 TABLE OF CONTENTS
Detailed Functional Block Diagram .............................................. 3 Specifications..................................................................................... 4 Analog Input ................................................................................. 4 Master Volume .............................................................................. 4 Programmable Gain Amplifier--ADC...................................... 4 Analog Mixer--Input Gain/Amplifiers/Attenuators............... 5 Digital Decimation and Interpolation Filters ........................... 5 Analog-to-Digital Converters..................................................... 5 Digital-to-Analog Converters..................................................... 5 Analog Output .............................................................................. 6 Static Digital Specifications......................................................... 6 Power Supply................................................................................. 6 Power-Down States ...................................................................... 7 Clock Specifications ..................................................................... 7 Timing Parameters ....................................................................... 8 Absolute Maximum Ratings.......................................................... 10 Environmental Conditions........................................................ 10 ESD Caution................................................................................ 10 Pin Configuration and Functional Descriptions........................ 11 Pin Descriptions ......................................................................... 11 Indexed Control Registers......................................................... 13 Outline Dimensions ....................................................................... 47 Ordering Guide........................................................................... 47
REVISION HISTORY
3/04--Data Sheet changed from Rev. 0 to Rev. A Updated Format.................................................................Universal Changes to Figure 1......................................................................... 1 Changes to Figure 2......................................................................... 3 Changes to Table 4........................................................................... 4 Changes to Tables 5, 7, and 8.......................................................... 5 Changes to Table 12 ........................................................................ 7 Changes to Pin Configuration..................................................... 11 Changes to Circuit Layout Note .................................................. 11 Changes to Indexed Control Registers ....................................... 13 Changes to Master Volume Register (Index 0x02).................... 15 Changes to Headphone Volume Register (Index 0x04) ........... 16 Changes to Mono Volume Register (Index 0x06) ..................... 17 Changes to PC Beep Register (Index 0x0A) .............................. 18 Changes to Microphone Volume Register (Index 0x0E).......... 19 Changes to AUX In Volume Register (Index 0x16) .................. 21 Changes to Record Select Control Register (Index 0x1A)....... 22 Changes to Record Gain Register (Index 0x1C) ....................... 23 Changes to Extended Audio ID Register (Index 0x28) ............ 27 Changes to Center/LFE Volume Control Register (Index 0x36).................................................................... 30 Changes to Surround Volume Control Register (Index 0x38) ................................................................................... 31 Changes to Jack Sense/Audio Interrupt/Status Register (Index 0x72) ................................................................................... 36 Changes to Miscellaneous Control Bits (Index 0x76) .............. 39 Changes to Advanced Jack Sense Register (Index 0x78).......... 41 Updated Outline Dimensions...................................................... 47 Updated Ordering Guide.............................................................. 47 3/03--Revision 0: Initial Version
Rev. A | Page 2 of 48
VREFOUT: 0x76 D3-D2 DEF=00 (+2.25V)
OMS: 0x74 D9 DEF=0(MIC_1/2)
M20: 0x0E D6 DEF=0 (0dB Gain) +2.25V MGB[1:0]: 0x76 D1-D0 DEF=0 (+20dB)
2CMIC: 0x76 D7 DEF=0 (MS Sel) MS: 0x20 D8 DEF=0 (MIC_1)
VREFOUT
00= 01= 10= 11=
+2.25V HIGH Z +3.7V 0V
VREF
XTL_OUT
XTL_IN SPDIF_OUT
MIC1 G SPDIF TX G
REC SELECTOR 0x1A D2-D0 RIGHT D10-D8 LEFT DEF=0x000 REC GAIN: 0x1C 0dB to +22.5dB DEF=0x8000 0dB/MUTED PCM ADC RATE: 0x32 7kHz-48kHz in 1Hz steps DEF 0xBB80 48kHz
0
AD1985
Z CODEC CORE PLL G VOLTAGE REFERENCE
PHONE_IN CD DIFF AMP G M
Left
OMS
1
2CMIC MS
MIC2
0
OMS
1 00= 01= 10= 11 +20dB Gain +10dB Gain +30dB Gain (reserved)
CD_L 16-BIT - ADC 16-BIT - ADC ADC SLOT LOGIC
ID0
CD_GND
CD_R G M
Right
AUX_L
ID1
AUX_R
LINE_IN_L
AC97 MODE: 0x18 ADI MODE: PCM VOL 0x36 +12dB to -34.5dB DEF 0x8808 0dB/MUTED PCM C/LFE DAC RATE: 0x30 7kHz-48kHz in 1Hz steps DEF 0xBB80 48kHz 1
000= 001= 010= 011= 100= 101= 110= 111= DSA: 0x28 D5-D4 DEF 00
MIC CD --AUX LINE_IN STR_MIX MON_MIX PHONE
LINE_IN_R
RESET
SPRD: 0x76 D6 AC97 MODE: C&LFE VOL 0x36 DEF=0 (NoSprd) ADI MODE: MASTER VOL 0x02 0dB to -46.5dB 0 LFE Right DEF 0x8000 0dB/MUTED LINE_IN VOL: 0x10 +12 to -34.5dB DEF=0x8808 0dB/MUTED
SYNC
0
SPRD
LFE_OUT
1 LFE Right DOWN MIX: 0x76 DMIX 1,0 (D9,D8) DEF=0x0 (MUTED) DOWN MIX: 0x76 DMIX 1,0 (D9,D8) DEF=0x0 (MUTED) 0 MIC VOL: 0x0E +12 to -34.5dB DEF=0x8808 0dB/MUTED
MZ A
CSWP
M
GA
20-BIT - DAC
DAC SLOT LOGIC
1
AC '97 INTERFACE V2.3
DETAILED FUNCTIONAL BLOCK DIAGRAM
BITCLK
0
OMS: 0x74 D9 DEF=0(MIC_1/2) CLDIS: 0x76 D11 DEF=0(enabled)
SPRD
Center Left
GA
Center Left
GA GA M M M M
AUX VOL: 0x16 +12 to -34.5dB DEF=0x8808 0dB/MUTED +0 to -45dB DEF=0x8000 0dB/MUTED
GA GA M M M GA M M GA
GA
GA
LODIS: 0x76 D12 DEF=0 (enabled) PHONE VOL: 0x0C +12 to -34.5dB DEF=0x8008 0dB/MUTED
Left
LOSEL
MIX
LODIS: 0x76 D12 DEF=0 (enabled)

M
DOWN MIX: 0x76 DMIX 1,0 (D9,D8) DEF=0x0 (MUTED)
Left
20-BIT - DAC M M GA GA
Right EQB
1 0
BYPASS
Right
LOSEL
0
1
0
20-BIT - DAC
EQ
1
BYPASS
AC97 MODE: SURR VOL 0x38 ADI MODE: HEADPHONE VOL 0x04 0dB to -46.5dB DEF 0x8000 0dB/MUTED
Left
HPSEL
SURR_OUT_L/ HP_OUT_L A
1
HP
M
AC97 MODE: 0x18 ADI MODE: PCM VOL 0x38 PCM SURR DAC RATE: 0x2E 7kHz-48kHz in 1Hz steps +12dB to -34.5dB DEF 0x8808 0dB/MUTED DEF 0xBB80 48kHz
AC '97 CONTROL REGISTERS
Note: Setting to enable Surround 5.1 is LOSEL=1
M M M
GA GA
20-BIT - DAC 20-BIT - DAC
EAPD: 0x26 D15 DEF=0 (Enabled)
JSENSE: 0x72 DEF=0x0000
SURR_OUT_R/ HP_OUT_R
0 HPSEL: 0x76 D10 DEF=0 (Surround)
Right
HPSEL
HP
M
A
HP STBY: PR6 reg 0x26 D14 1=power down, DEF=0
G = GAIN A = ATTENUATION M = MUTE Z = HIGH Z
EAPD
ANALOG MIXING CONTROL JACK SENSE
AD1985
03610-A-002
EAPD JS0 JS1 JS2 JS3
EQ COEF STORAGE
Figure 2. Detailed Functional Block Diagram
M M
AUX VOL: 0x16 +12 to -34.5dB DEF=0x8808 0dB/MUTED 1
Rev. A | Page 3 of 48
A
1
LINE_OUT: MASTER VOL 0x02 0dB to -46.5dB DEF=0x8000 0dB/MUTED 1 0
LOSEL: 0x76 D5 DEF=0 (Mixer)
M
M
CSWP: 0x74 D3 DEF=0 (NoCSwp)
LINE_OUT_L
MZ
A
MONO_OUT: MONO VOL 0x06 0dB to -46.5dB DEF=0x8000 0dB/MUTED
MIX: 0x20 D9 DEF=0 (Mixer)
PCBeep: 0x0A Vol: D4-D0 Mute: D15 Frequency: D12-D5
MONO_OUT A
0
M
CD VOL: 0x012 +12 to -34.5dB DEF=0x8008 0dB/MUTED
CSWP
CENTER_OUT
MZ
M
GA
20-BIT - DAC
SDATA_OUT M A PC BEEP GENERATOR
PCM VOL: 0x18 +12dB to -34.5dB DEF 0x8808 0dB/MUTED PCM FRONT DAC RATE: 0x2C 7kHz-48kHz in 1Hz steps DEF 0xBB80 48kHz EQB: 0x72 D9-D8 DEF=0 (EQ Enabled) 0
LINE_OUT: MASTER VOL 0x02 0dB to -46.5dB DEF=0x8000 0dB/MUTED 1
LOSEL: 0x76 D5 DEF=0 (Mixer)
EQ
SDATA_IN
LINE_OUT_R A
MZ
AD1985 SPECIFICATIONS
Table 1. Test Conditions, Unless Otherwise Noted
Parameter TEMPERATURE DIGITAL SUPPLY (DVDD) ANALOG SUPPLY (AVDD) SAMPLE RATE (fS) INPUT SINE WAVE SIGNAL ANALOG OUTPUT PASS BAND DAC TEST CONDITIONS Value/Condition Unit 25 C 3.3 V 5.0 V 48 kHz 1,008 Hz 20 to 20,000 Hz Calibrated Output -3 dB relative to full scale 10 k output load: line 32 output load: headphone 2 k output load: center and LFE 47.5 k output load: mono Calibrated 0 dB PGA gain Input -3 dB relative to full scale 24.576 MHz
ADC TEST CONDITIONS
CLOCK
ANALOG INPUT
Table 2.
Parameter INPUT VOLTAGE LINE_IN, CD, AUX, PHONE_IN MIC_IN with +30 dB Preamp MIC_IN with +20 dB Preamp MIC_IN with +10 dB Preamp MIC_IN with 0 dB Preamp Input Impedance1 Input Capacitance1 Min Typ 1 2.83 0.032 0.089 0.1 0.283 0.316 0.894 1 2.83 20 5 Max Unit V rms V p-p V rms V p-p V rms V p-p V rms V p-p V rms V p-p k pF
7.5
MASTER VOLUME
Table 3.
Parameter STEP SIZE (LINE OUT, MONO OUT, SURROUND OUT, CENTER, LFE) OUTPUT ATTENUATION RANGE (0 dB TO -46.5 dB) MUTE ATTENUATION OF 0 dB FUNDAMENTAL1 Min Typ 1.5 46.5 Max Unit dB dB dB
80
PROGRAMMABLE GAIN AMPLIFIER--ADC
Table 4.
Parameter STEP SIZE (0 dB TO +22.5 dB) PGA GAIN RANGE Min Typ 1.5 22.5 Max Unit dB dB
1
Guaranteed, not tested. Rev. A | Page 4 of 48
AD1985
ANALOG MIXER--INPUT GAIN/AMPLIFIERS/ATTENUATORS
Table 5.
Parameter SIGNAL-TO-NOISE RATIO (SNR) CD to LINE_OUT LINE, AUX, PHONE, to LINE_OUT MIC1 or MIC2 to LINE_OUT Step Size: All Mixer Inputs, Except PC Beep Input Gain/Attenuation Range (+12 dB to -34.5 dB): All Mixer Inputs, Except PC Beep Min Typ 90 85 80 1.5 46.5 Max Unit dB dB dB dB dB
DIGITAL DECIMATION AND INTERPOLATION FILTERS1
Table 6.
Parameter PASS BAND PASS-BAND RIPPLE TRANSITION BAND STOP BAND STOP-BAND REJECTION GROUP DELAY GROUP DELAY VARIATION OVER PASS BAND Min 0 0.4 x fS 0.6 x fS -74 16/fS 0 Typ Max 0.4 x fS 0.09 0.6 x fS Unit Hz dB Hz Hz dB s s
ANALOG-TO-DIGITAL CONVERTERS
Table 7.
Parameter RESOLUTION TOTAL HARMONIC DISTORTION (THD) DYNAMIC RANGE (-60 dB IN; THD+N REFERENCED TO FULL-SCALE; A-WEIGHTED) SIGNAL-TO-INTERMODULATION DISTORTION (CCIF METHOD)1 ADC CROSSTALK1 Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) LINE_IN to Other GAIN ERROR (FULL-SCALE SPAN RELATIVE TO NOMINAL INPUT VOLTAGE) INTERCHANNEL GAIN MISMATCH (DIFFERENCE OF GAIN ERRORS) ADC OFFSET ERROR1 Min Typ 16 -85 84 85 -85 -95 10 0.5 5 Max Unit Bits dB dB dB dB dB % dB mV
DIGITAL-TO-ANALOG CONVERTERS
Table 8.
Parameter RESOLUTION TOTAL HARMONIC DISTORTION (THD); LINE_OUT, C/LFE TOTAL HARMONIC DISTORTION (THD); HP_OUT DYNAMIC RANGE (-60 dB IN; THD+N REFERENCED TO FULL-SCALE; A-WEIGHTED) SIGNAL-TO-INTERMODULATION DISTORTION (CCIF METHOD)1 GAIN ERROR (OUTPUT FULL-SCALE VOLTAGE RELATIVE TO NOMINAL OUTPUT FULL-SCALE VOLTAGE)2 INTERCHANNEL GAIN MISMATCH (DIFFERENCE OF GAIN ERRORS) DAC CROSSTALK (INPUT L, ZERO R, READ R_OUT; INPUT R, ZERO L, READ L_OUT)1 TOTAL OUT-OF-BAND ENERGY (MEASURED FROM 0.6 x fS TO 100 KHZ)1 Min Typ 20 -90 -75 90 100 10 -100 -85 Max Unit Bits dB dB dB dB % dB dB dB
0.7
1 2
Guaranteed, not tested. C/LFE specified with 10 k load.
Rev. A | Page 5 of 48
AD1985
ANALOG OUTPUT
Table 9.
Parameter FULL-SCALE OUTPUT VOLTAGE: LINE OUT, MONO OUT, CENTER, LFE Output Impedance1 External Load Impedance1 Output Capacitance1 External Load Capacitance FULL-SCALE OUTPUT VOLTAGE: HP_OUT External Load Capacitance1 External Load Impedance1 VREF VREFOUT (VREFH, VREFD = 00 in REGISTER 0x76) VREFOUT (VREFH, VREFD = 10) VREFOUT (VREFH, VREFD = 11) VREFOUT CURRENT DRIVE MUTE CLICK (MUTED OUTPUT UNMUTED MIDSCALE DAC OUTPUT) Min Typ 1 2.83 300 10 15 1 2.83 1000 32 2.1 2.25 2.25 3.70 0.0 5 2.4 Max Unit V rms V p-p k pF pF V rms V p-p pF V V V V mA mV
500
2
1000
5
Note that setting VREFOUT to 0 V reduces crosstalk when Center/LFE is sharing the MIC jack. The Center/LFE crosstalk should be better than -60 dB at 100 Hz when sharing with a stereo microphone application circuit.
STATIC DIGITAL SPECIFICATIONS
Table 10.
Parameter DIGITAL INPUTS/OUTPUTS High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Output Voltage (VOH), IOH = 2 mA Low Level Output Voltage (VOL), IOL = 2 mA INPUT LEAKAGE CURRENT OUTPUT LEAKAGE CURRENT INPUT/OUTPUT PIN CAPACITANCE Min 0.65 x DVDD 0.35 x DVDD 0.9 x DVDD -10 -10 0.1 x DVDD +10 +10 7.5 Typ Max Unit V V V V A A pF
POWER SUPPLY
Table 11.
Parameter POWER SUPPLY RANGE--ANALOG (AVDD) POWER SUPPLY RANGE--DIGITAL (DVDD) POWER DISSIPATION--5 V/3.3 V POWER SUPPLY REJECTION (100 mV p-p SIGNAL @ 1 kHz)1 Min 4.5 2.97 Typ Max 5.5 3.63 Unit V V mW dB
465 40
1
Guaranteed, not tested.
Rev. A | Page 6 of 48
AD1985
POWER-DOWN STATES1
Table 12.
Parameter FULL POWER-UP ADC FRONT DAC CENTER DAC SURROUND DAC LFE DAC ADC + ALL DACs MIXER ADC + MIXER ALL DACS + MIXER ADC + ALL DACS + MIXER STANDBY HEADPHONE STANDBY PR[K:I]2 000 000 000 001 010 100 111 000 000 111 111 111 000 PR[6:0]2 000 0000 000 0001 000 0010 000 0000 000 0000 000 0000 000 0011 000 0100 000 0101 000 0110 000 0111 011 1111 100 0000 I DVDD (3.3 V) Typ 55.5 47.4 49.5 55.5 49.0 55.1 15.8 55.5 47.4 34.1 14.3 0.114 55.5 I AVDD (5 V) Typ 56.0 49.9 47.9 56.0 47.5 56.0 24.2 34.3 27.4 10.0 2.5 0.004 48.3 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA
CLOCK SPECIFICATIONS
Table 13.
Parameter INPUT CLOCK FREQUENCY (XTAL MODE OR CLOCK OSCILLATOR) INPUT CLOCK FREQUENCY (REFERENCE CLOCK MODE) INPUT CLOCK FREQUENCY (USB CLOCK MODE) RECOMMENDED CLOCK DUTY CYCLE Min Typ 24.576 14.31818 48.000 50 Max Unit MHz MHz MHz %
40
60
1 2
Currents measured with VREFOUT unloaded. PR bits are controlled in Registers 0x2A and 0x26.
Rev. A | Page 7 of 48
AD1985
TIMING PARAMETERS
Guaranteed over operating temperature range. Table 14.
Parameter RESET ACTIVE LOW PULSE WIDTH RESET INACTIVE TO SDATA_IN OR BIT_CLK ACTIVE DELAY SYNC ACTIVE HIGH PULSE WIDTH SYNC LOW PULSE WIDTH SYNC INACTIVE TO BIT_CLK STARTUP DELAY BIT_CLK FREQUENCY BIT_CLK PERIOD BIT_CLK OUTPUT JITTER1, 2 BIT_CLK HIGH PULSE WIDTH BIT_CLK LOW PULSE WIDTH SYNC FREQUENCY SYNC PERIOD SETUP TO FALLING EDGE OF BIT_CLK HOLD FROM FALLING EDGE OF BIT_CLK BIT_CLK RISE TIME BIT_CLK FALL TIME SYNC RISE TIME SYNC FALL TIME SDATA_IN RISE TIME SDATA_IN FALL TIME SDATA_OUT RISE TIME SDATA_OUT FALL TIME END OF SLOT 2 TO BIT_CLK, SDATA_IN LOW SETUP TO TRAILING EDGE OF RESET (APPLIES TO SYNC, SDATA_OUT) RISING EDGE OF RESET TO HIGH-Z DELAY PROPAGATION DELAY RESET RISE TIME OUTPUT VALID DELAY FROM RISING EDGE OF BIT_CLK TO SDI VALID RESET INACTIVE TO BIT_CLK STARTUP DELAY Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF 33 33 Min 162.8 1.3 19.5 162.8 12.288 81.4 750 42 38 48.0 20.8 2.5 4 4 4 4 4 4 4 4 Typ 1.0 Max Unit s ns s s ns MHz ns ps ns ns kHz s ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns ns
2000 48 48
10 5 2 2 2 2 2 2 2 2 0 15.0
6 6 6 6 6 6 6 6 1.0 25.0 15 50 15 25
tCO tTRI2ACTV
1 2
Guaranteed, not tested. Output jitter directly dependent on crystal input jitter; maximum specified for noncrystal operation.
Rev. A | Page 8 of 48
AD1985
tRST2CLK tRST_LOW
RESET
tTRI2ACTV
BIT_CLK
tTRI2ACTV
SDATA_IN
Figure 3. Cold Reset Timing (Codec is Supplying the Bit_CLK Signal)
tSYNC_HIGH
SYNC
tSYNC2CLK
BIT_CLK
Figure 4. Warm Reset Timing
tCLK_LOW
SYNC SLOT 1 SLOT 2
BIT_CLK
tCLK_HIGH tCLK_PERIOD
BIT_CLK
SDATA_OUT
tSYNC_LOW
SYNC
03610-0-005
WRITE TO 03 26
DATA PR4
03610-0-004
03610-0-003
tS2_PDOWN
SDATA_IN
03610-0-007
tSYNC_HIGH tSYNC_PERIOD
BIT_CLK NOT TO SCALE
Figure 7. AC Link Low Power Mode Timing
Figure 5. Clock Timing
tCO tSETUP
BIT_CLK
BIT_CLK VIH VIL
tRISECLK
tFALLCLK
SDATA_OUT VOH
03610-0-008
SYNC
SDATA_IN SYNC
VOL
tRISESYNC
tFALLSYNC
tHOLD
SDATA_IN
Figure 8. AC Link Low Power Mode Timing
tRISEDIN tFALLDIN
RESET
03610-0-006
SDATA_OUT
SDATA_OUT
tRISEDOUT
tFALLDOUT
tSETUP2RST
Hi-Z
03610-0-009
Figure 6. Signal Rise and Fall Times
SDATA_IN, BIT_CLK, EAPD, SPDIF_OUT AND DIGITAL I/O
tOFF
Figure 9. ATE Test Mode
Rev. A | Page 9 of 48
AD1985 ABSOLUTE MAXIMUM RATINGS
Table 15.
Parameter POWER SUPPLIES Digital (DVDD) Analog (AVDD) INPUT CURRENT (EXCEPT SUPPLY PINS) ANALOG INPUT VOLTAGE (SIGNAL PINS) DIGITAL INPUT VOLTAGE (SIGNAL PINS) AMBIENT TEMPERATURE (OPERATING) STORAGE TEMPERATURE Min Max -0.3 +3.6 -0.3 +6.0 10.0 -0.3 AVDD + 0.3 Unit V V mA V
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating
TCASE = Case Temperature in C PD = Power Dissipation in W JA = Thermal Resistance (Junction to Ambient) JC = Thermal Resistance (Junction to Case)
-0.3 DVDD + 0.3 V 0 -65 70 +150 C C
Table 16. Thermal Resistance
Package Type LQFP JA 50.1C/W JC 17.8C/W
All measurements per EIA/JESD51 with 2S2P test board per EIA/JESD51-7.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 10 of 48
AD1985 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SURR/HP_OUT_R SURR/HP_OUT_L MONO_OUT AVDD3 AVDD2 SPDIF AVSS3 AVSS2 EAPD
ID1
ID0
48 47 46 45 44 43 42 41 40 39 38 37
NC
DVDD1 1 XTL_IN 2 XTL_OUT 3 DVSS1 4 SDATA_OUT 5 BIT_CLK 6 DVSS2 7 SDATA_IN 8 DVDD2 9 SYNC 10 RESET 11 JS3 12
36 PIN 1 IDENTIFIER 35 34 33
LINE_OUT_R (FRONT)/SURR_R LINE_OUT_L (FRONT)/SURR_L AVDD4 JS2 LFE_OUT CENTER_OUT AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1 NC = NO CONNECT
AD1985
TOP VIEW (Not to Scale)
32 31 30 29 28 27 26 25
13 14 15 16 17 18 19 20 21 22 23 24
JS1
PHONE_IN
AUX_R
AUX_L
JS0
CD_GND_REF
LINE_IN_R
LINE_IN_L
MIC1
CD_R
CD_L
MIC2
Figure 10. 48-Lead LQFP Pin Configuration
Circuit Layout Note: In normal operation, Surround and Line Out are swapped to provide headphone drive on line outputs. Therefore, Pins 35 and 36 become the surround L/R outputs and Pins 39 and 41 become the Line Out (Front) L/R outputs with headphone drive. See Bits LOSEL and HPSEL in Register 0x76 for details.
PIN FUNCTION DESCRIPTIONS
Table 17. Digital I/O
Mnemonic XTL_IN XTL_OUT SDATA_OUT BIT_CLK SDATA_IN SYNC RESET SPDIF Pin No. 2 3 5 6 8 10 11 48 I/O I O I O/I O I I O Description Crystal Input (24.576 MHz) or External Clock In (24.576 MHz, 14.31818 MHz, or 48.000 MHz). Crystal Output. AC Link Serial Data Output. AD1985 input stream. AC Link Bit Clock. 12.288 MHz serial data clock. (Input pin, for secondary mode only.) AC Link Serial Data Input. AD1985 output stream. AC Link Frame Sync. AC Link Reset. AD1985 master hardware reset. SPDIF Output.
Table 18. Chip Selects/Clock Strapping
Mnemonic ID0 ID1 Pin No. 45 46 I/O I I Description Chip Select Input 0 (Active Low). This pin can also be used as the chain input from a secondary codec. Chip Select Input 1 (Active Low).
Table 19. Jack Sense/EAPD
Mnemonic EAPD JS0 JS1 JS2 JS3 Pin No. 47 17 16 33 12 Type O I I I I Description EAPD Output. JACK SENSE 0 Input. JACK SENSE 1 Input. JACK SENSE 2 Input. JACK SENSE 3 Input.
Rev. A | Page 11 of 48
03610-A-011
AD1985
Table 20. Analog I/O
Mnemonic PHONE_IN AUX_L AUX_R CD_L CD_GND_REF CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R CENTER_OUT LFE_OUT LINE_OUT_L/SURR_L LINE_OUT_R/SURR_R MONO_OUT SURR_OUT_L/HP_OUT_L SURR_OUT_R/HP_OUT_R Pin No. 13 14 15 18 19 20 21 22 23 24 31 32 35 36 37 39 41 I/O I I I I I I I I I I I/O I/O O O O O O Description Monaural Line-Level Input. Auxiliary Input, Left Channel. Auxiliary Input, Right Channel. CD Audio Left Channel. CD Audio Analog Ground Reference for Differential CD Input. CD Audio Right Channel. Microphone 1 Input. Microphone 2 Input. Line In Left Channel. Line In Right Channel. Center Channel Output or Input to Recorder (depending on OMS bit in Reg 0x74). Low Frequency Enhanced Output or Input to Recorder (depending on OMS bit in Reg 0x74). Line Out (Front) Left Channel or Surround Left Channel (depending on LOSEL bit in Reg 0x76). Line Out (Front) Right Channel or Surround Right Channel (depending on LOSEL bit in Reg 0x76). Monaural Output to Telephony Subsystem Speakerphone. Surround or Front Headphone Left Channel Output (depending on HPSEL bit in Reg 0x76). Surround or Front Headphone Right Channel Output (depending on HPSEL bit in Reg 0x76).
Table 21. Filter/Reference
Mnemonic VREF VREFOUT AFILT1 AFLIT2 Pin No. 27 28 29 30 I/O O O O O Description Voltage Reference Filter. Voltage Reference Output (Intended for Mic Bias). Antialiasing Filter Capacitor--ADC Right Channel. Antialiasing Filter Capacitor--ADC Left Channel.
Table 22. Power and Ground Signals
Mnemonic DVDD1 DVSS1 DVSS2 DVDD2 AVDD1 AVSS1 AVDD4 AVDD2 AVSS2 AVDD3 AVSS3 Pin No. 1 4 7 9 25 26 34 38 40 43 44 Type I I I I I I I I I I I Description Digital VDD: 3.3 V. Digital Ground. Digital Ground. Digital VDD: 3.3 V. Analog VDD: 5.0 V. Analog Ground. Analog VDD: 5.0 V. Analog VDD: 5.0 V. Analog Ground. Analog VDD: 5.0 V. Analog Ground.
Table 23. No Connects
Mnemonic NC Pin No. 42 Type N/A Description No Connect.
Rev. A | Page 12 of 48
AD1985
INDEXED CONTROL REGISTERS
Reg Name D15
X MM HPM MVM PCBM PHM MCM LM CM AM OM X IM X I4 EAPD AID1
D14
SE4 X X X X X X X X X X X X X I3 PR6 AID0
D13
SE3 X X X X X X X X X X X X X I2 PR5 X PRK SRF13 SRS13
D12
SE2 LMV4 LHV4 X PCBF7 X X LLV4 LCV4 LAV4 LOV4 X X X I1 PR4 X PRJ SRF12 SRS12
D11
SE1 LMV3 LHV3 X PCBF6 X X LLV3 LCV3 LAV3 LOV3 X LIV3 DRSS1 I0 PR3 REV1 PRI SRF11 SRS11
D10
SE0 LMV2 LHV2 X PCBF5 X X LLV2 LCV2 LAV2 LOV2 LS2 LIV2 DRSS0 X PR2 REV0 SPCV SRF10 SRS10
D9
ID9 LMV1 LHV1 X
D8
ID8 LMV0 LHV0 X
D7
ID7 MMRM1 HPRM1 X PCBF2 X X LVRM1 CDRM1 AVRM1 OMRM1 X IMRM1 LPBK X X
D6
ID6 X X X PCBF1 X M20 X X X X X X X X X
D5
ID5 X X X PCBF0 X X X X X X X X X X X
D4
ID4 RMV4 RHV4 MV4 PCBV3 PHV4 MCV4 RLV4 RCV4 RAV4 ROV4 X X X X X DSA0 SPSA0 SRF4 SRS4 SRCL4 SRA4 CNT4 RSR4 CC0 BCA4 CFD4 X JS0 MD INTS SRU JS2MD VIDS4
D3
ID3 RMV3 RHV3 MV2 PCBV2 PHV3 MCV3 RLV3 RCV3 RAV3 ROV3 X RIV3 X PG3 REF X X SRF3 SRS3 SRCL3 SRA3 CNT3 RSR3 PRE BCA3 CFD3 X JS1 ST CSWP VREFH JS3ST VIDS3
D2
ID2 RMV2 RHV2 MV2 PCBV1 PHV2 MCV2 RLV2 RCV2 RAV2 ROV2 RS2 RIV2 X PG2 ANL
D1
ID1 RMV1 RHV1 MV1 PCBV0 PHV1 MCV1 RLV1 RCV1 RAV1 ROV1 RS1 RIV1 X PG1 DAC
D0
ID0 RMV0 RHV0 MV0 X PHV0 MCV0 RLV0 RCV0 RAV0 ROV0 RS0 RIV0 X PG0 ADC AIDVRA
Default
0x0090 0x8000 0x8000 0x8000 0x8000 0x8008 0x8008 0x8808 0x8808 0x8808 0x8808 0x0000 0x8000 0x0000 0xXXXX N/A 0xXBC7
0x00 Reset 0x02 Master Volume 0x04 Headphones Volume 0x06 Mono Volume 0x0A PC Beep 0x0C Phone_In Volume 0x0E MIC Volume 0x10 Line In Volume 0x12 CD Volume 0x16 AUX In Volume 0x18 PCM Out Vol 0x1A Record Select 0x1C Record Gain 0x20 General Purpose 0x24 Audio Int. and Paging 0x26 Power-Down Ctrl/Stat 0x28 Extended Audio ID 0x2A Ext'd Audio Stat/Ctrl 0x2C PCM Front DAC Rate 0x2E PCM Surr DAC Rate 0x30 PCM LFE/C DAC Rate 0x32 PCM L/R ADC Rate 0x36 Center/LFE volume 0x38 Surround Volume 0x3A SPDIF Control 0x60 EQ Control 0x62 EQ Data 0x70 J Sense/General 0x72 J Sense/Audio/Status 0x74 Serial Configuration 0x76 Misc Control Bits 0x78 Advanced Jack Sense 0x7C Vendor ID1 0x7E Vendor ID2 0x60 Codec Class/Rev pg. 1 0x62 PCI SVID pg. 1 0x64 PCI SID pg. 1 0x66 Function Select pg. 1 0x68 Function Information pg. 1 0x6A Sense Register pg. 1
PCBF4 PCBF3 X X LLV1 LCV1 LAV1 LOV1 LS1 LIV1 MIX X PR1 X X LLV0 LCV0 LAV0 LOV0 LS0 LIV0 MS X PR0
AMAP AIDLDAC AIDSDAC AIDCDAC DSA1 X SRF9 SRS9 ASCLDAC ASCSDAC ASCCDAC SPSA1 SRF8 SRS8 SRF7 SRS7 SRCL7 SRA7 CNTM RSM CC3 SYM CFD7 MMDIS JS1 TMR SPOVR SPRD JS3TMR VIDS7 VIDREV7 RV7 PVI7 PI7 X DL2 OR1 SRF6 SRS6 SRCL6 SRA6 X X CC2 CHS CFD6 JS2SEL JS0 TMR LBKS1 2CMIC JS2TMR VIDS6 VIDREV6 RV6 PVI6 PI6 X DL1 OR0 SRF5 SRS5 SRCL5 SRA5 X RSR5 CC1 BCA5 CFD5 X JS1 MD LBKS0 LOSEL JS3MD VIDS5
AIDSPDIF DRA
VFORCE X SRF15 SRS15 SRF14 SRS14
ASCSPDF ASCDRA ASCVRA 0xXXXX SRF2 SRS2 SRCL2 SRA2 CNT2 RSR2 COPY BCA2 CFD2 X JS0 ST SPAL VREFD JS2ST VIDS2 SRF1 SRS1 SRCL1 SRA1 CNT1 RSR1 AUD BCA1 CFD1 X JS1 INT SPDZ MBG1 JS3INT VIDS1 SRF0 SRS0 SRCL0 SRA0 CNT0 RSR0 PRO BCA0 CFD0 X JS0 INT SPLNK MBG0 JS2INT VIDS0 0xBB80 0xBB80 0xBB80 0xBB80 0x8080 0x8080 0x2000 0x8080 0x0000 N/A N/A 0x1001 0x0000 N/A 0x4144
SRCL15 SRCL14 SRA15 LFEM LSM V EQM CFD15 X JS SPRD SRA14 X X X X CFD14 X JS1 DMX
SRCL13 SRCL12 SRCL11 SRCL10 SRCL9 SRCL8 SRA13 X LSR5 SPSR1 X CFD13 X JS0 DMX SRA12 LFE4 LSR4 SPSR0 X CFD12 X JS MT2 SRA11 LFE3 LSR3 L X CFD11 X JS MT1 SRA10 LFE2 LSR2 CC6 X CFD10 X JS MT0 SRA9 LFE1 LSR1 CC5 X CFD9 X JS1 EQB OMS SRA8 LFE0 LSR0 CC4 X CFD8 X JS0 EQB CHEN
SLOT16 REGM2 DACZ X VIDF7 VIDT7 X PVI15 PI15 X G4 ST2
REGM1 REGM0 REGM3 DRF LODIS X VIDF4 VIDT4 CL4 PVI12 PI12 X G1 S4 CLDIS X VIDF3 VIDT3 CL3 PVI11 PI11 X G0 S3 HPSEL X VIDF2 VIDT2 CL2 PVI10 PI10 X INV S2
AC97NC MSPLT X VIDF6 VIDT6 X PVI14 PI14 X G3 ST1 X VIDF5 VIDT5 X PVI13 PI13 X G2 ST0
DMIX1 DMIX0 X VIDF1 VIDT1 CL1 PVI9 PI9 X DL4 S1 X VIDF0 VIDT0 CL0 PVI8 PI8 X DL3 S0
VIDREV5 VIDREV4 VIDREV3 VIDREV2 RV5 PVI5 PI5 X DL0 SR5 RV4 PVI4 PI4 FC3 IV SR4 RV3 PVI3 PI3 FC2 X SR3 RV2 PVI2 PI2 FC1 X SR2
VIDREV1 VIDREV0 0x5375 RV1 PVI1 PI1 FC0 X SR1 RV0 PVI0 PI0 T/R FIP SR0 N/A N/A N/A 0x0000 N/A N/A
NOTES Odd register addresses are aliased to the next lower even address. Registers not shown and bits containing an X are assumed to be reserved. Reserved registers should not be written. Zeros should be written to reserved bits.
1
For AC `97 compatibility, these RM bits must be enabled before they can have any effect.
Rev. A | Page 13 of 48
AD1985
Reset (Index 0x00)
Reg Num 0x00 Name Reset D15 X D14 SE4 D13 SE3 D12 SE2 D11 SE1 D10 SE0 D9 ID9 D8 ID8 D7 ID7 D6 ID6 D5 ID5 D4 ID4 D3 ID3 D2 ID2 D1 ID1 D0 ID0 Default 0x0090
Note: Writing any value to this register performs a register reset, which causes all registers (except Register 0x74) to revert to their default values. Register 0x74 will only reset Bits CSWP (D3), LBKS[1:0] (D[6:5]), and OMS (D9). The REGM and serial configuration bits are reset only by an external hardware reset. Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.
ID[9:0] Identify Capability: The ID decodes the capabilities of AD1985 based on the following:
Bit = 1 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 Function Dedicated MIC PCM In Channel Reserved (per AC '97, 2.3) Bass and Treble Control Simulated Stereo (Mono to Stereo) Headphone Out Support Loudness (Bass Boost) Support 18-Bit DAC Resolution 20-Bit DAC Resolution 18-Bit ADC Resolution 20-Bit ADC Resolution AD1985 0 0 0 0 1 0 0 1 0 0
SE[4:0] Stereo Enhancement. The AD1985 does not provide hardware 3D stereo enhancement (all bits are 0).
Rev. A | Page 14 of 48
AD1985
Master Volume Register (Index 0x02)
Reg Num Name 0x02 Master Volume D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 1 MM X X LMV4 LMV3 LMV2 LMV1 LMV0 MMRM X X RMV4 RMV3 RMV2 RMV1 RMV0 0x8000
1 For AC '97 compatibility, Bit D7 (MMRM) is available only by setting the MSPLT bit in Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
This register controls the LINE_OUT volume and mute bits. Each volume subregister contains five bits, generating 32 volume levels with increments of 1.5 dB each. AC '97 defines the 6-bit volume registers, therefore, to maintain compatibility whenever the D5 or D13 bit is set to 1, its respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1.
Note that depending on the state of the AC97NC bit in Register 0x76, this register has the following additional functionality: * For AC97NC = 0, the register controls the LINE_OUT output attenuators only. * For AC97NC = 1, the register controls the LINE_OUT, center, and LFE output attenuators.
RMV[4:0] MMRM LMV[4:0] MM
Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Right Channel Mute. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the MM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Master Volume Mute. When this bit is set to 1, all channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in which case, this mute bit will only affect the left channels.
Volume Settings for Master and Headphone
Reg. 0x76 MSPLT1 0 0 0 0 0 1 1 1 D15 0 0 0 0 1 0 1 1 Control Bits Master Volume (0x02) and Headphone Volume (0x04) Left Channel Volume D[13:8] Right Channel Volume D[5:0] 1 Write Readback Function D7 Write Readback Function 00 0000 0 dB Gain x 00 0000 0 dB Gain 00 00 0000 0000 00 1111 -22.5 dB Gain x 00 1111 -22.5 dB Gain 00 00 1111 1111 01 1111 -46.5 dB Gain x 01 1111 -46.5 dB Gain 01 01 1111 1111 1x xxxx 01 1111 -46.5 dB Gain x 1x xxxx 01 1111 -46.5 dB Gain xx xxxx xx xxxx - dB Gain, Muted x xx xxxx xx xxxx - dB Gain, Muted 1x xxxx 01 1111 -46.5 dB Gain 1 xx xxxx xx xxxx - dB Gain, Only Right Muted xx xxxx xx xxxx 0 1x xxxx 01 1111 -46.5 dB Gain - dB Gain, Only Left Muted xx xxxx xx xxxx - dB Gain, Left Muted 1 xx xxxx xx xxxx - dB Gain, Right Muted
Note: x in the above table is a wild card, meaning the value has no effect.
1 For AC '97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect.
Rev. A | Page 15 of 48
AD1985
Headphone Volume Register (Index 0x04)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 1 0x04 Headphones Volume HPM X X LHV4 LHV3 LHV2 LHV1 LHV0 HPRM X X RHV4 RHV3 RHV2 RHV1 RHV0 0x8000
1
For AC '97 compatibility, Bit D7 (HPRM) is available only by setting the MSPLT bit in Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
This register controls the headphone volume for both stereo channels and mute bits. Each volume subregister contains five bits, generating 32 volume levels with increments of 1.5 dB each. AC '97 defines the 6-bit volume registers, therefore, to maintain compatibility whenever the D5 or D13 bit is set to 1, its respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1 (see the Volume Settings for
Master and Headphone table on the previous page). Note that depending on the state of the AC97NC bit in Register 0x76, this register has the following additional functionality: * For AC97NC = 0, the register has no control over the SURR_OUT/HP_OUT outputs (see Register 0x38). * For AC97NC = 1, the register controls the SURR_OUT/HP_OUT output attenuators.
RHV[4:0] HPRM LHV[4:0] HPM
Right Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Right Channel Mute. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the HPM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. Left Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Headphones Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in which case, this mute bit will only affect the left channel.
Rev. A | Page 16 of 48
AD1985
Mono Volume Register (Index 0x06)
Reg Num 0x06 Name Mono Volume D15 MVM D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default X X X X X X X X X X MV4 MV3 MV2 MV1 MV0 0x8000
This register controls the mono output volume and mute bit. The volume register contains five bits, generating 32 volume levels with increments of 1.5 dB each.
AC '97 defines the 6-bit volume registers, therefore, to maintain compatibility whenever the D5 bit is set to 1, its respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever this bit is set to 1.
MV[4:0] MVM
Mono Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Mono Volume Mute. When this bit is set to 1, the channel is muted.
Volume Settings for Mono
D15 0 0 0 1 Control Bits D[4:0] for Mono (0x06) Write Readback 0 0000 0 0000 0 1111 0 1111 1 1111 1 1111 x xxxx x xxxx Function 0 dB Gain -22.5 dB Gain -46.5 dB Gain - dB Gain, Muted
Note that the x in the above table is a wild card, meaning the value has no effect.
Rev. A | Page 17 of 48
AD1985
PC Beep Register (Index 0x0A)
Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x0A PC Beep Volume PCBM X X PCBF7 PCBF6 PCBF5 PCBF4 PCBF3 PCBF2 PCBF1 PCBF0 PCBV3 PCBV2 PCBV1 PCBV0 X 0x8000
This register controls the level and frequency for the digital PC beep generated by the codec. Please note that PC Beep should be muted when not in use.
PCBV[3:0] PCBF[7:0]
Controls the volume of the generated signal. Each step corresponds to approximately 3 dB of attenuation. The MSB of the register is the mute bit. When this bit is set to 1, the level for the signal is set at - dB. These bits are writeable, and the codec-digital PC beep generation is supported. The beep frequency generated is the result of dividing the 48 kHz clock by 4x the number specified in PCBF[7:0], allowing tones from 47 Hz to 12 kHz. A value of 0x00 in Bits PCBF[7:0] disables internal PC beep generation. The PV bits control the volume level of the generated signal.
The register default value is 0x8000, which corresponds to 0 dB attenuation with mute on.
PCBM 0 0 1
PV3 to PV0 0000 1111 xxxx
Function 0 dB Attenuation 45 dB Attenuation dB Attenuation
PCBF 0x00 0x01 0x0C 0xFF
Frequency of PC Beep PC Beep Disabled 12 kHz 1 kHz 47 Hz
Rev. A | Page 18 of 48
AD1985
Phone_In Volume Register (Index 0x0C)
Reg Num 0x0C Name Phone_In Volume D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default PHM X X X X X X X X X X PHV4 PHV3 PHV2 PHV1 PHV0 0x8008
PHV[4:0] PHM
Phone Volume. Allows setting the phone volume gain/attenuator to one of 32 levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, with mute bit enabled. Phone Mute. When this bit is set to 1, the Phone channel is muted.
Volume Settings for Phone and MIC
Control Bits D[4:0] Phone (0x0C) and MIC (0x0E) Write Readback 0 0000 0 0000 0 1000 0 1000 1 1111 1 1111 x xxxx x xxxx
D15 0 0 0 1
Function 12 dB Gain 0 dB Gain -34.5 dB Gain - dB Gain, Muted
Note that the x in the above table is a wild card, meaning the value has no effect.
Microphone Volume Register (Index 0x0E)
Reg Num 0x0E Name MIC Volume D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MCM X X X X X X X X M20 X MCV4 MCV3 MCV2 MCV1 MCV0 Default 0x8008
This register controls the volume, gain boost, and mute for the gain/attenuators on both the MIC1 and MIC2 paths to the mixer. There is no separate control for left and right on this path. The signal paths must be identical, hence the single control for both.
MCV[4:0] M20
MCM
MIC Volume. Allows setting the MIC volume gain/attenuator to one of 32 levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, with mute enabled. MIC Gain Boost. This bit allows setting additional MIC gain to increase the microphone sensitivity. Gain is applied to the microphone path to both the analog mixer and the ADC(s). The nominal gain boost by default is +20 dB; however, Bits D0 and D1 (MBG[1:0]) on the Miscellaneous Control Bits Register (0x76), allow changing the gain boost to +10 dB or +30 dB, if necessary. 0 = Disabled; Gain = 0 dB. 1 = Enabled; Default Gain = +20 dB (see Register 0x76, Bits D0 and D1). MIC Mute. When this bit is set to 1, both channels are muted.
Rev. A | Page 19 of 48
AD1985
Line In Volume (Index 0x10)
Reg Num 0x10 Name Line In Volume D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 1 LM X X LLV4 LLV3 LLV2 LLV1 LLV0 LVRM X X RLV4 RLV3 RLV2 RLV1 RLV0 0x8808
1
For AC '97 compatibility, Bit D7 (LVRM) is available only by setting the MSPLT bit in Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
RLV[4:0] LVRM LLV[4:0] LM
Right Line In Volume. Allows setting the line in right channel gain/attenuator to one of 32 levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the LM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. Line In Volume Left. Allows setting the line in left channel gain/attenuator to one of 32 levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Line In Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in which case, this mute bit will affect only the left channel.
Volume Settings for Line In, CD Volume, AUX, and PCM Out
Reg. 0x76 MSPLT1 0 0 0 0 1 1 1 D15 0 0 0 1 0 1 1 Write 0 0000 0 1000 1 1111 x xxxx 1 1111 x xxxx x xxxx Control Bits Line In (0x10), CD (0x12), AUX (0x16), and PCM Out (0x18) Left Channel Volume D[12:8] Right Channel Volume D[4:0] Readback Function Readback Function D71 Write 0 0000 12 dB Gain x 0 0000 0 0000 12 dB Gain 0 1000 0 dB Gain x 0 1000 0 1000 0 dB Gain 1 1111 -34.5 dB Gain x 1 1111 1 1111 -34.5 dB Gain x xxxx - dB Gain, Muted x x xxxx x xxxx - dB Gain, Muted 1 1111 -34.5 dB Gain 1 x xxxx x xxxx - dB Gain, Only Right Muted x xxxx - dB Gain, Only Left Muted 0 1 1111 1 1111 -34.5 dB Gain x xxxx - dB Gain, Left Muted 1 x xxxx x xxxx - dB Gain, Right Muted
1 For AC '97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect. Note that the x in the above table is a wild card, meaning the value has no effect.
CD Volume Register (Index 0x12)
Reg Num 0x12 Name CD Volume D15 D14 D13 D12 D11 D10 D9 D8 D7 CM X X LCV4 LCV3 LCV2 LCV1 LCV0 CDRM1 D6 D5 D4 D3 D2 D1 D0 Default X X RCV4 RCV3 RCV2 RCV1 RCV0 0x8808
1 For AC97 compatibility, Bit D7 (CDRM) is available only by setting the MSPLT bit in Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. See the Volume Settings for Line In, CD Volume, AUX, and PCM Out table.
RCV[4:0] CDRM LCV[4:0] CM
Right CD Volume. Allows setting the CD right channel gain/attenuator to one of 32 levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the CM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. Left CD Volume. Allows setting the CD left channel gain/attenuator to one of 32 levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. CD Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in which case, this mute bit will only affect the left channel.
Rev. A | Page 20 of 48
AD1985
AUX In Volume Register (Index 0x16)
Reg Num 0x16 Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 1 AUX In Volume AM X X LAV4 LAV3 LAV2 LAV1 LAV0 AVRM X X RAV4 RAV3 RAV2 RAV1 RAV0 0x8808
1 For AC '97 compatibility, Bit D7 (AVRM) is available only by setting the MSPLT bit in Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. See the Volume Settings for Line In, CD Volume, AUX, and PCM Out table.
RAV[4:0] AVRM LAV[4:0] AM
Right AUX Volume. Allows setting the AUX right channel gain/attenuator to one of 32 levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute: Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the AM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. Left AUX Volume. Allows setting the AUX left channel gain/attenuator to one of 32 levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. AUX Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in which case, this mute bit will only affect the left channel.
PCM Out Volume (Index 0x18)
Reg Num 0x18 Name PCM Out Vol D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default OM X X LOV4 LOV3 LOV2 LOV1 LOV0 OMRM1 X X ROV4 ROV3 ROV2 ROV1 ROV0 0x8808
1
For AC '97 compatibility, Bit D7 (OMRM) is available only by setting the MSPLT bit in Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. See the Volume Settings for Line In, CD Volume, AUX, and PCM Out table. Note that depending on the state of the AC97NC bit in Register 0x76, this register has the following additional functionality: * For AC97NC = 0, the register also controls the surround, center, and LFE DAC gain/attenuators. * For AC97NC = 1, the register controls the PCM out volume only.
ROV[4:0] OMRM LOV[4:0] OM
Right PCM Out Volume. Allows setting the PCM right channel gain/attenuator to one of 32 levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the OM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. Left PCM Out Volume. Allows setting the PCM left channel gain/attenuator to one of 32 levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. PCM Out Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in which case, this mute bit will only affect the left channel.
Rev. A | Page 21 of 48
AD1985
Record Select Control Register (Index 0x1A)
Reg Num 0x1A Name Record Select D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X LS2 LS1 LS0 X X X X X RS2 RS1 RS0 Default 0x0000
This register is used to select the record source, independently for the right and left channels. For single MIC recording, see the MS bit (Register 0x20) for MIC1 and MIC2 input selection. For dual MIC recording, see the 2CMIC bit (Register 0x76) to enable simultaneous recording into L/R channels. For output line sharing for the microphones, see the OMS bit (Register 0x74) to swap between the MIC1/MIC2 and C/LFE pins. The default value is 0x0000, which corresponds to the MIC input for both channels.
RS[2:0] LS[2:0]
Right Record Select: See table below. Left Record Select: See table below.
LS[2:0]
0
1 2 3 4 5 6 7 RS[2:0]
0
1 2 3 4 5 6 7
Left Record Select OMS 2CMIC MS 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 CD_IN (left) Muted AUX_IN (left) LINE_IN (left) Stereo Mix (left) Mono Mix (mono) PHONE_IN (mono) Right Record Select OMS 2CMIC MS 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 CD_IN (right) Muted AUX_IN (right) LINE_IN (right) Stereo Mix (right) Mono Mix (mono) PHONE_IN (mono)
MIC1 (mono) MIC2 (mono) MIC1 (stereo) MIC2 (stereo) CENTER (mono) LFE (mono) CENTER (stereo) LFE (stereo)
MIC1 (mono) MIC2 (mono) MIC2 (stereo) MIC1 (stereo) CENTER (mono) LFE (mono) LFE (stereo) CENTER (stereo)
Rev. A | Page 22 of 48
AD1985
Record Gain Register (Index 0x1C)
Reg Num 0x1C Name Record Gain D15 D14 D13 D12 D11 IM X X X LIV3 D10 LIV2 D9 LIV1 D8 LIV0 D7 IMRM1 D6 D5 D4 D3 X X X RIV3 D2 RIV2 D1 RIV1 D0 RIV0 Default 0x8000
1 For AC '97 compatibility, Bit D7 (IMRM) is available only by setting the MSPLT bit in Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
RIV[3:0] IMRM LIV[3:0] IM
ADC Right Channel Input Volume Gain Control. Each LSB represents 1.5 dB and the gain range is 0 dB to +22.5 dB. Right Channel Mute. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the IM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. ADC Left Channel Input Volume Gain Control. Each LSB represents 1.5 dB and the gain range is 0 dB to +22.5 dB. Input Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in Register 0x76 is set to 1, in which case, this mute bit will only affect the left channel.
IM 0 0 1
xIM[3:0] 1111 0000 xxxxx
Function +22.5 dB Gain 0 dB Gain Muted
Rev. A | Page 23 of 48
AD1985
General Purpose Register (Index 0x20)
Reg Num 0x20 Name General Purpose D15 D14 D13 D12 D11 X X X X DRSS1 D10 DRSS0 D9 D8 D7 MIX MS LPBK D6 D5 D4 D3 D2 D1 D0 Default X X X X X X X 0x0000
LPBK
MS
Loopback Control. This bit enables the digital internal loopback from the ADC to the front DAC. This feature is normally used for testing and troubleshooting. See LBKS bits in Register 0x74 for changing the loopback path to use the surround or center/LFE DACs. MIC Select. Selects MIC input into the record selector input and also selects the input to the analog mixer. (See the 2CMIC [Bit D7 Register 0x76] to enable simultaneous dual microphone recording, and the OMS [Bit D9 Register 0x74] to enable output line sharing for the microphone inputs.) The following chart shows which of the codec I/O pins are used for the microphone source from the various settings of the microphone control bits. OMS 2CMIC MS Left Channel Right Channel 0 0 0 MIC1 (mono) MIC1 (mono) 0 0 1 MIC2 (mono) MIC2 (mono) 0 1 0 MIC1 (stereo) MIC2 (stereo) 0 1 1 MIC2 (stereo) MIC1 (stereo) 1 0 0 CENTER (mono) CENTER (mono) 1 0 1 LFE (mono) LFE (mono) 1 1 0 CENTER (stereo) LFE (stereo) 1 1 1 LFE (stereo) CENTER (stereo) Mono Output Select. Selects mono output audio source. 0 = Mixer Output. Default. 1 = Selected MIC Channel (Selected Channel Is Unaffected by 2CMIC Setting). MIX OMS MS Mono Output 0 X X Mixer_mono (default) 1 0 0 MIC1 (mono) 1 0 1 MIC2 (mono) 1 1 0 CENTER (mono) 1 1 1 LFE (mono) Double Rate Slot Select. The DRSS bits specify the slots for the n + 1 sample outputs. PCM L (n + 1) and PCM R (n + 1) data are by default provided in output slots 10 and 11. 00: PCM L, R n + 1 data is on slots 10, 11 (reset default). 01: PCM L, R n + 1 data is on slots 7, 8. 10: Reserved. 11: Reserved.
MIX
DRSS[1:0]
Rev. A | Page 24 of 48
AD1985
Audio Interrupt and Paging Mechanism Register (Index 0x24)
Reg Num 0x24 Name Audio Int. and Paging D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default I4 I3 I2 I1 I0 X X X X X X X PG3 PG2 PG1 PG0 0xXXXX
Note that this register controls the audio interrupt and register paging mechanisms.
I4
I[3:2]
I1
I0
X PG[3:0]
Interrupt Status (Read/Write), Default Is 0. 0: Interrupt is clear. 1: Interrupt was generated. Interrupt event is cleared by writing a 1 to this bit. The interrupt status bit will change regardless of the setting of interrupt enable (I0). An interrupt in the GPI in Slot 12 in the AC link will follow this bit change when interrupt enable (I0) is unmasked. If this bit is set, one or both of I3 or I2 must be set to indicate the interrupt cause. Interrupt Cause (Read-Only), Default Is 0. I[2] = 0: Sense status has not changed (did not cause interrupt). I[2] = 1: Sense cycle completed or new sense information is available. I[3] = 0: GPIO status change did not cause interrupt (default) I[3] = 1: GPIO status change caused interrupt. These bits will indicate the cause(s) of an interrupt. This information should be used to service the correct interrupting event(s). If the interrupt status bit (I4) is set, one or both of these bits must be set to indicate the interrupt cause. Hardware resets these bits back to 0 when the interrupt status bit is cleared. Sense Cycle (Read/Write), Default Is 0. 0: Sense cycle not in progress. 1: Sense cycle start. Writing a 1 to this bit causes a sense cycle start if supported. If a sense cycle is in progress, writing a 0 to this bit will abort the sense cycle. The data in the sense result register (0x6A, Page 1) may or may not be valid, as determined by the IV bit in that register. Interrupt Enable (Read/Write), Default Is 0. 0: Interrupt generation is masked. 1: Interrupt generation is unmasked. Software should not unmask the interrupt unless the AC '97 controller ensures that no conflict is possible with modem Slot 12-- GPI functionality. AC '97 2.2 compliant controllers will not likely support audio codec interrupt infrastructure. In that case, software can poll the interrupt status after initiating a sense cycle and waiting for the Sense Cycle Maximum Delay (which is defined by the software) to determine if an interrupting event has occurred. Reserved. Page Selector (Read/Write), Default Is 0x0. 0: Vendor Specific. 0x1: Page ID 01, registers defined in AC'97, Rev. 2.3. 0x2 to 0xF: Reserved Pages. This register is used to select a descriptor of 16-word pages between Registers 0x60 and 0x6F. A value of 0x0 is used to select vendor specific space to maintain compatibility with AC '97 2.2 vendor specific registers. System software can determine implemented pages by writing the page number and reading the value back. If the value read back does not match the value written, the page is not implemented. All implemented pages must be in consecutive order, i.e., Page 0x2 cannot be implemented without Page 0x1.
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AD1985
Power-Down Control/Status Register (Index 0x26)
Reg Num 0x26 Name Power-Down Ctrl/Stat D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC N/A
Note that the ready bits are read-only; writing to REF, ANL, DAC, and ADC will have no effect. These bits indicate the status for the AD1985 subsections. If the bit is a 1, then that subsection is ready. Ready is defined as the subsection able to perform in its nominal state.
ADC DAC ANL REF PR[6:0] PR0 PR1 PR2 PR3
PR4
PR5
PR6 EAPD
ADC Sections Ready to Transmit Data. DAC Sections Ready to Accept Data. Analog Amplifiers, Attenuators, and Mixers Ready. Voltage References, VREF and VREFOUT, Up to Nominal Level. Codec Power-Down Modes. Some bits can be used individually, while others are used in combination. ADCs and Input Mux Power-Down. Default setting is 0. Clearing this bit will enable VREF, regardless of the state of PR3. DACs Power-Down. Also powers down the EQ circuitry. Default setting is 0. Clearing this bit will enable VREF, regardless of the state of PR3. Mixer Power-Down. Default setting is 0. Power Down VREF and VREFOUT. Default setting is 0. May be used in combination with PR2 or by itself. If all the ADCs and DACs are not powered down, setting this bit will have no effect on the VREF, and it will only power down VREFOUT. AC Link Interface Power-Down. Default setting is 0. The reference and the mixer can be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set. In multiple-codec systems, the master codec's PR4 bit controls the slave codec. In the slave codec, the PR4 bit has no effect, except to enable or disable PR5. Internal Clocks Disabled. Default setting is 0. PR5 has no effect, unless all ADCs, DACs, and the AC link are powered down, e.g., PR0, PR1, PR4. The reference and the mixer can be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set. In multiple codec systems, the master codec's PR5 controls the slave codec. PR5 is effective in the slave codec if the master's PR5 bit is clear. Powers Down the Headphone Amplifiers. Default setting is 0. External Audio Power-Down Control. Controls the state of the EAPD pin. EAPD = 0 sets the EAPD pin low, enabling an external power amplifier. (Reset default.) EAPD = 1 sets the EAPD pin high, shutting the external power amplifier off.
PR0 = 1
PR1 = 1
PR2 = 1
PR4 = 1
NORMAL
ADCs OFF PR0
DACs OFF PR1
ANALOG OFF PR2 OR PR3
DIGITAL I/F OFF PR4
SHUT OFF AC-LINK
PR0 = 0 AND ADC = 1
PR1 = 0 AND DAC = 1
PR2 = 0 AND ANL = 1
WARM RESET
READY = 1 DEFAULT
COLD RESET
Figure 11. Example of AC '97 Power-Down/Power-Up Flow
Rev. A | Page 26 of 48
AD1985
Extended Audio ID Register (Index 0x28)
Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Num 0x28 Extended AID1 AID0 X X REV1 REV0 AMAP AIDLDAC AIDSDAC AIDCDAC DSA1 DSA0 X AIDSPDIF DRA Audio ID D0 Default
AIDVRA 0xXBC7
The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates that one or more of the extended audio features are supported.
AIDVRA AIDSPDIF DRA DSA[1:0]
AIDCDAC AIDSDAC AIDLDAC AMAP REV[1:0] AID[1:0]
Variable Rate PCM Audio Support (Read-Only). This bit returns a 1 when read to indicate that variable rate PCM audio is supported. SPDIF Support (Read-Only). This bit returns a 1 when read to indicate that SPDIF transmitter is supported (IEC958). Double Rate Audio (Read-Only). This bit returns a 1 when read to indicate that the optional double rate PCM audio is supported for PCM L and PCM R. DAC Slot Assignments. (Read/Write; Reset Default = 00.) 00: DACs 1, 2 = 3 and 4 DACs 3, 4 = 7 and 8 DACs 5, 6 = 6 and 9 01: DACs 1, 2 = 7 and 8 DACs 3, 4 = 6 and 9 DACs 5, 6 = 10 and 11 10: DACs 1, 2 = 6 and 9 DACs 3, 4 = 10 and 11 DACs 5, 6 = 3 and 4 11: DACs 1, 2 = 10 and 11 DACs 3, 4 = 3 and 4 DACs 5, 6 = 7 and 8 PCM Center DAC Support (Read-Only). This bit returns a 1 when read to indicate that PCM Center DAC is supported. PCM Surround DAC Support (Read-Only). This bit returns a 1 when read to indicate that PCM surround left and right DACs are supported. PCM LFE DAC Support (Read-Only). This bit returns a 1 when read to indicate that PCM LFE DAC is supported. Slot DAC Mappings Based on Codec ID (Read-Only). This bit returns a 1 when read to indicate that slot/DAC mappings based on codec ID is supported. REV[1:0] = 10 Indicates That Codec Is AC '97 Revision 2.3 Compliant (Read-Only). Indicates Codec Configuration (Read-Only). 00 = Primary. 01, 10, 11 = Secondary.
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AD1985
Extended Audio Status and Control Register (Index 0x2A)
Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Num 0x2A Extended VFORCE X PRK PRJ PRI SPCV X ASCLDAC ASCSDAC ASCCDAC SPSA1 SPSA0 X ASCSPDF ASCDRA ASCVRA 0xXXXX Audio Stat/Ctrl
The extended audio status and control register is a read/write register that provides status and control of the extended audio features.
ASCVRA
ASCDRA
ASCSPDF
SPSA[1,0]
ASCCDAC ASCSDAC ASCLDAC SPCV
PRI PRJ PRK VFORCE
Variable Rate Audio (Read/Write). ASCVRA = 0 sets fixed sample rate audio at 48 kHz (reset default). ASCVRA = 1 enables variable rate audio mode (enables sample rate registers and AC '97 SLOTREQ signaling). Double Rate Audio. ASCDRA = 1 enables double-rate audio mode in which data from PCM L and PCM R in output Slots 3 and 4 is used in conjunction with PCM L (n + 1) and PCM R (n + 1) data to provide DAC streams at twice the sample rate designated by the PCM Front Sample Rate Control Register. When using the double rate audio only the front DACs are supported, and all other DACs (surround, center and LFE) are automatically powered down. Note that ASCDRA can be used without ASCVRA; in that case, the converter rates are forced to 96 kHz if ASCDRA = 1. SPDIF Transmitter Subsystem Enable/Disable Bit (Read/Write). ASCSPDF = 1 enables the SPDIF transmitter. ASCSPDF = 0 disables the SPDIF transmitter (default). This bit is also used to validate that the SPDIF transmitter output is actually enabled. The ASCSPDF bit is only allowed to be set high if the Pin 48 (SPDIF) is pulled down at power-up, enabling the codec transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled, and therefore, the ASCSPDF bit returns a low, indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter is actually enabled. SPDIF Slot Assignment Bits (Read/Write). These bits control the SPDIF slot assignment and respective defaults, depending on the codec ID configuration (see the the AC `97 2.3 AMAP Compliant Default SPDIF Slot Assignments table for more information.) Center DAC Status (Read-Only). ASCCDAC = 1 indicates the PCM center DAC is ready. Surround DAC Status. (Read-only.) ASCSDAC = 1 Indicates the PCM surround DACs are ready. LFE DAC Status (Read-Only). ASCLDAC = 1 indicates the PCM LFE DAC is ready. SPDIF Configuration Valid (Read-Only). Indicates the status of the SPDIF transmitter subsystem, enabling the driver to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent of the SPDIF enable bit status. SPCV = 0 indicates current SPDIF configuraton (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported). SPCV = 1 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (is supported). Center DAC Power-Down (Read/Write). PRI = 1 mutes the PCM center DAC. Essentially, PRI + PRK = powered off center/LFE DACs. Surround DACs Power-Down (Read/Write). PRJ = 1 turns off the PCM surround DACs. LFE DAC Power-Down (Read/Write). PRK = 1 mutes the PCM LFE DAC. Essentially, PRI + PRK = powered off center/LFE DACs. Validity Force Bit. (Reset Default = 0). When asserted, this bit forces the SPDIF stream Validity flag (Bit <28> within each SPDIF L/R subframe) to be controlled by the V bit (D15) in Register 0x3A (SPDIF control register). VFORCE = 0 and V = 0: The Validity bit is managed by the codec error detection logic. VFORCE = 0 and V = 1: The Validity bit is forced high, indicating subframe data is invalid. VFORCE = 1 and V = 0: The Validity bit is forced low, indicating subframe data is valid. VFORCE = 1 and V = 1: The Validity bit is forced high, indicating subframe data is invalid.
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AD1985
AC `97 2.3 AMAP Compliant Default SPDIF Slot Assignments
Codec ID 00 00 00 01 01 10 10 11 Function 2-ch Primary with SPDIF 4-ch Primary with SPDIF 6-ch Primary with SPDIF +2-ch Secondary with SPDIF +4-ch Secondary with SPDIF +2-ch Secondary with SPDIF +4-ch Secondary with SPDIF +2-ch Secondary with SPDIF SPSA = 00 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 SPSA = 01 7 and 8 [default] 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 SPSA = 10 6 and 9 6 and 9 (default) 6 and 9 6 and 9 (default) 6 and 9 6 and 9 (default) 6 and 9 6 and 9 SPSA = 11 10 and 11 10 and 11 10 and 11 (default) 10 and 11 (default) 10 and 11 (default) 10 and 11 (default)
PCM Front DAC Rate Register (Index 0x2C)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x2C PCM Front DAC Rate SRF15 SRF14 SRF13 SRF12 SRF11 SRF10 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF1 SRF0 0xBB80
This read/write sample rate control register contains 16-bit unsigned values, representing the rate of operation in Hz.
SR[15:0]
Sample Rate. The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. The codec may not function correctly if frequencies are written outside this range. If 0 is written to ASCVRA (Reg 0x2A), then the sample rate is reset to 48 kHz.
PCM Surround DAC Rate Register (Index 0x2E)
Reg Num Name 0x2E PCM Surr DAC Rate D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default SRS15 SRS14 SRS13 SRS12 SRS11 SRS10 SRS9 SRS8 SRS7 SRS6 SRS5 SRS4 SRS3 SRS2 SRS1 SRS0 0xBB80
This read/write sample rate control register contains 16-bit unsigned values, representing the rate of operation in Hz. This register sets the sample rate for the Surround DAC. This register's reset default is to be locked to the PCM front DAC sample rate register (0x2C). To unlock this register, Bit SSRU in Register 0x76 must be asserted.
SRS[15:0] Sample Rate. The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. The codec may not function correctly if frequencies are written outside this range. If 0 is written to ASCVRA (Reg 0x2A), then the sample rate is reset to 48 kHz.
PCM LFE/Center DAC Rate Register (Index 0x30)
Reg Num NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x30 PCM LFE/C DAC SRCL15 SRCL14 SRCL13 SRCL12 SRCL11 SRCL10 SRCL9 SRCL8 SRCL7 SRCL6 SRCL5 SRCL4 SRCL3 SRCL2 SRCL1 SRCL0 0xBB80 Rate
This read/write sample rate control register contains 16-bit unsigned values, representing the rate of operation in Hz. This register sets the sample rate for the LFE DAC and center DAC. This register's reset default is to be locked to the PCM front DAC sample rate register (0x2C). To unlock this register, Bit SSRU in Register 0x76 must be asserted.
SRCL[15:0] Sample Rate. The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. The codec may not function correctly if frequencies are written outside this range. If 0 is written to ASCVRA (Register 0x2A), then the sample rate is reset to 48 kHz.
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AD1985
PCM L/R ADC Rate Register (Index 0x32)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x32 PCM L/R ADC Rate SRA15 SRA14 SRA13 SRA12 SRA11 SRA10 SRA9 SRA8 SRA7 SRA6 SRA5 SRA4 SRA3 SRA2 SRA1 SRA0 0xBB80
This read/write sample rate control register contains 16-bit unsigned values, representing the rate of operation in Hz.
SR[15:0] Sample Rate. The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. The codec may not function correctly if frequencies are written outside this range. If 0 is written to ASCVRA (Register 0x2A), then the sample rate is reset to 48 kHz.
Center/LFE Volume Register (Index 0x36)
Reg Num 0x36 Name Center/LFE Volume D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default LFEM X X LFE4 LFE3 LFE2 LFE1 LFE0 CNTM X X CNT4 CNT3 CNT2 CNT1 CNT0 0x8080
This register controls the center and LFE output volumes and mute bits. The volume register contains five bits, generating 32 volume levels with increments of 1.5 dB each. AC '97 defines the 6-bit volume registers, therefore, to maintain compatibility whenever the D5 or D13 bit is set to 1, its respective lower five volume bits are automatically set to 1 by codec logic. On read-back, all lower five bits will read 1s whenever this bit is set to 1.
Note that depending on the state of the AC 97NC bit in Register 0x76, this register operates as follows: * For AC'97NC = 0, the register controls the center and LFE output pin attenuators. The range is 0 dB to -46.5 dB. * For AC97NC = 1, the register controls the center and LFE DAC gain/attenuators. The range is +12 dB to -34.5 dB.
CNT[4:0] CNTM LFE[4:0] LFEM
Center Volume Control. Center Volume Mute. When this bit is set to 1, the channel is muted. LFE Volume Control. LFE Volume Mute. When this bit is set to 1, the channel is muted.
Note that when the CSWP bit (Register 0x74) is set to 1, the definition of these volume controls for left and right are swapped, i.e., LFE[4:0] and LFEM control center volume/mute, and CNT[4:0] and CNTM control LFE volume/mute.
CNTM (LFEM) 0 0 0 0 1
Write 00 0000 00 1111 01 1111 1x xxxx xx xxxx
CNT/LFE[5:0] Readback 00 0000 00 1111 01 1111 01 1111 xx xxxx
Function with AC97NC = 0 0 dB Gain -22.5 dB Gain -46.5 dB Gain -46.5 dB Gain Muted, - dB Gain
Function with AC97NC = 1 +12 dB Gain -10.5 dB Gain -34.5 dB Gain Indeterminate1 Muted, - dB Gain
Note: x in the above table is a wild card, meaning the value has no effect.
1
When AC97NC is set to 1, there is only a 5-bit gain/attenuator to control, so the sixth bit, i.e., the MSB, does not control anything. Therefore, the 5-bit gain setting is indeterminate, since the five LSBs are listed as wild cards.
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AD1985
Surround Volume Control Register (Index 0x38)
Reg Num 0x38 Name Surround Volume D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default LSM X LSR5 LSR4 LSR3 LSR2 LSR1 LSR0 RSM X RSR5 RSR4 RSR3 RSR2 RSR1 RSR0 0x8080
This register controls the surround volume controls for both stereo channels and mute bits. Each volume subregister contains five bits, generating 32 volume levels with increments of 1.5 dB each. AC '97 defines the 6-bit volume registers, therefore, to maintain compatibility whenever the D5 or D13 bit is set to 1, its respective lower five volume bits are automatically set to 1 by the codec logic. On read-back, all lower five bits will read 1s whenever these bits are set to 1.
Note that depending on the state of the AC97NC bit in Register 0x76, this register operates as follows: * For AC97NC = 0, the register controls the surround output pin attenuators. The range is 0 dB to -46.5 dB. * For AC97NC = 1, the register controls the surround DAC gain/attenuators. The range is +12 dB to -34.5 dB.
RSR[5:0] RSM LSR[5:0] LSM
Right Surround Volume Control. Right Surround Volume Mute. When this bit is set to 1, the right channel is muted. Left Surround Volume Control. Left Surround Volume Mute. When this bit is set to 1, the left channel is muted.
LSM (RSM) 0 0 0 0 1
Write 00 0000 00 1111 01 1111 1x xxxx xx xxxx
xSR[5:0] Readback 00 0000 00 1111 01 1111 01 1111 xx xxxx
Function with AC97NC = 0 0 dB Gain -22.5 dB Gain -46.5 dB Gain -46.5 dB Gain Muted, - dB Gain
Function with AC97NC = 1 +12 dB Gain -10.5 dB Gain -34.5 Gain Indeterminate1 Muted, - dB Gain
Note: x in the above table is a wild card, meaning the value has no effect.
1
When AC97NC is set to 1, there is only a 5-bit gain/attenuator to control, so the sixth bit, i.e., the MSB, does not control anything. Therefore, the 5-bit gain setting is indeterminate, since the five LSBs are listed as wild cards.
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AD1985
SPDIF Control Register (Index 0x3A)
Reg.Num. 0x3A Name SPDIF Control D15 D14 D13 V X D12 D11 D10 D9 SPSR1 SPSR0 L D1 D0 Default CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY AUD PRO 0x2000 D8 D7 D6 D5 D4 D3 D2
Register 0x3A is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in Register 0x2A is 0). This ensures that control and status information initialize correctly at the beginning of SPDIF transmission.
PRO AUD COPY PRE CC[6:0] L SPSR[1:0]
Professional. 1 indicates professional use of channel status, 0 indicates consumer. Nonaudio. 1 indicates data is nonPCM format, 0 indicates data is PCM. Copyright. 1 indicates copyright is asserted, 0 indicates copyright is not asserted. Pre-emphasis. 1 indicates filter pre-emphasis is 50/15 s, 0 indicates no pre-emphasis. Category Code. Programmed according to IEC standards, or as appropriate. Generation Level. Programmed according to IEC standards, or as appropriate. SPDIF Transmit Sample Rate. SPSR[1:0] = 00: Transmit Sample Rate = 44.1 kHz. SPSR[1:0] = 01: Reserved. SPSR[1:0] = 10: Transmit Sample Rate = 48 kHz (default). SPSR[1:0] = 11: Not supported. Validity. This bit affects the Validity flag (Bit <28> transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to maintain connection during error or mute conditions. V = 1: Each SPDIF subframe (L+R) has Bit <28> set to 1. This tags both samples as invalid. V = 0: Each SPDIF subframe (L+R) has Bit <28> set to 0 for valid data and 1 for invalid data (error condition). Note that when V = 0, asserting the VFORCE bit (D15) in Register 0x2A (Extended Audio Stat/Ctrl) will force the Validity flag low, marking both samples as valid.
V
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AD1985
EQ Control Register (Index 0x60)
Reg.Num. 0x60 Name EQ Control D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default EQM X X X X X X X SYM CHS BCA5 BCA4 BCA3 BCA2 BCA1 BCA0 0x8080
Register 0x60 is a read/write register that controls equalizer function and data setup. The register also contains the biquad and coefficient address pointer, which is used in conjunction with the EQ data register (0x78) to set up the equalizer coefficients. The reset default disables the equalizer function
BCA[5:0]
until the coefficients can be properly set up by the software and sets the symmetry bit to allow equal coefficients for left and right channels.
CHS SYM
EQM
Biquad and Coefficient Address Pointer: biquad 0 coef a0 BCA[5:0] = 011011 biquad 0 coef a1 BCA[5:0] = 011010 biquad 0 coef a2 BCA[5:0] = 011001 biquad 0 coef b1 BCA[5:0] = 011101 biquad 0 coef b2 BCA[5:0] = 011100 biquad 1 coef a0 BCA[5:0] = 100000 biquad 1 coef a1 BCA[5:0] = 011111 biquad 1 coef a2 BCA[5:0] = 011110 biquad 1 coef b1 BCA[5:0] = 100010 biquad 1 coef b2 BCA[5:0] = 100001 biquad 2 coef a0 BCA[5:0] = 100101 biquad 2 coef a1 BCA[5:0] = 100100 biquad 2 coef a2 BCA[5:0] = 100011 biquad 2 coef b1 BCA[5:0] = 100111 biquad 2 coef b2 BCA[5:0] = 100110 biquad 3 coef a0 BCA[5:0] = 101010 biquad 3 coef a1 BCA[5:0] = 101001 biquad 3 coef a2 BCA[5:0] = 101000 biquad 3 coef b1 BCA[5:0] = 101100 biquad 3 coef b2 BCA[5:0] = 101011 biquad 4 coef a0 BCA[5:0] = 101111 biquad 4 coef a1 BCA[5:0] = 101110 biquad 4 coef a2 BCA[5:0] = 101101 biquad 4 coef b1 BCA[5:0] = 110001 biquad 4 coef b2 BCA[5:0] = 110000 biquad 5 coef a0 BCA[5:0] = 110100 biquad 5 coef a1 BCA[5:0] = 110011 biquad 5 coef a2 BCA[5:0] = 110010 biquad 5 coef b1 BCA[5:0] = 110110 biquad 5 coef b2 BCA[5:0] = 110101 biquad 6 coef a0 BCA[5:0] = 111001 biquad 6 coef a1 BCA[5:0] = 111000 biquad 6 coef a2 BCA[5:0] = 110111 biquad 6 coef b1 BCA[5:0] = 111011 biquad 6 coef b2 BCA[5:0] = 111010 Channel Select. CHS = 0: Selects left channel coefficients data block. CHS = 1: Selects right channel coefficients data block. Symmetry. When set to 1 this bit indicates that the left and right channel coefficients are equal. This shortens the coefficient setup sequence since only the left channel coefficients need to be addressed and set up. (The right channel coefficients are simultaneously copied into memory.) Equalizer Mute. When set to 1, this bit disables the equalizer function (allows all data to pass through). The reset default sets this bit to 1, disabling the equalizer function until the biquad coefficients can be properly set.
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AD1985
EQ Data Register (Index 0x62)
Reg.Num. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x62 EQ Data CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0x0000
This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the BCA bits in the EQ control register (0x60). Data will be written to memory only if the EQM bit (Register 0x60, Bit 15) is asserted.
CFD[15:0]
Coefficient Data. The biquad coefficients are fixed-point format values with 16 bits of resolution. The CFD15 bit is the MSB and the CFD0 bit is the LSB.
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AD1985
Jack Sense/General Register (Index 0x70)
Reg Num 0x70 Name J Sense/General D15 D14 D13 D12 D11 D10 D9 D8 D7 X X X X X X X X MMDIS D6 JS2SEL D5 D4 D3 D2 D1 D0 Default X X X X X X N/A
JS2SEL
MMDIS
X
Selects JS2 Input Behavior. 0: Standard operation for JS2 jack sensing (default). 1: Enable microphone input sensing with JS2. Mono Mute Disable. 0: Use JSMT[2:0] (Register 0x72) to determine mono out operation (default). 1: Independent of the settings in the JSMT table, this ensures mono out remains active all the time. Reserved, Do Not Read/Write These Bits.
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AD1985
Jack Sense/Audio Interrupt/Status Register (Index 0x72)
Reg Num Name 0x72 Jack Sense/ Audio/Status D15 JS SPRD D14 JS1 DMX D13 JS0 DMX D12 D11 D10 D9 JS JS JS JS1 MT2 MT1 MT0 EQB D8 JS0 EQB D7 JS1 TMR D6 JS0 TMR D5 JS1 MD D4 JS0 MD D3 D2 D1 JS1 JS0 JS1 ST ST INT D0 JS0 INT Default N/A
Note: All register bits are read/write except for JS0ST and JS1ST, which are read-only.
JS0INT
JS1INT JS0ST JS1ST JS0MD
JS1MD
JS0TMR JS1TMR JS0EQB JS1EQB JSMT[2:0] JS0DMX
JS1DMX JSSPRD
Indicates Pin JS0 has generated an interrupt. Remains set until the software services the JS0 interrupt; i.e., JS0 ISR (Interrupt Service Routine) should clear this bit by writing a 0 to it. Notes: 1) Interrupts are generated by valid state changes of JS pins. 2) Interrupt to the system is actually an OR combination of this bit and JS3INT to JS0INT. 3) The interrupt implementation path is selected by the INTS bit (Register 0x74). 4) It is also possible to generate a software system interrupt by writing a 1 to this bit. Indicates Pin JS1 has generated an interrupt. Remains set until the software services the JS1 interrupt; i.e., JS1 ISR (Interrupt Service Routine) should clear this bit by writing a 0 to it. See JS0INT description above for additional details. JS0 State. This bit always reports the logic state of the JS0 pin. Cannot be used for MIC sensing. JS1 State. This bit always reports the logic state of the JS1 pin. Cannot be used for MIC sensing. JS0 Mode. This bit selects the operation mode for the JS0 pin. 0: Jack Sense Mode (Reset Default). 1: Interrupt Mode. JS1 Mode: This bit selects the operation mode for the JS1 pin. 0: Jack Sense Mode (Reset Default). 1: Interrupt Mode. JS0 Timer Enable. If this bit is set to a 1, JS0 must be high for greater than 298 ms to be recognized. JS1 Timer Enable. If this bit is set to a 1, JS1 must be high for greater than 298 ms to be recognized. JS0 EQ Bypass Enable. This bit enables JS0 to control the EQ bypass. When this bit is set to 1, JS0 = 1 will cause the EQ to be bypassed. Default is 0. JS1 EQ Bypass Enable. This bit enables JS1 to control the EQ bypass. When this bit is set to 1, JS1 = 1 will cause the EQ to be bypassed. Default is 0. JS Mute Enable Selector. These three bits select and enable the jack sense muting action (see theJack Sense Mute Select (JSMT [2:0]) table). JS0 Down-Mix Control Enable. This bit enables JS0 to control the down-mix function. This function allows a digital mix of 6-channel audio into 2-channel audio. The mix can then be routed to the stereo LINE_OUT or HP_OUT jacks. When this bit is set to 1, JS0 = 1 will activate the down-mix conversion. See the DMIX description in Register 0x76. The DMIX bits select the down-mix implementation type and can also force the function to be activated. JS1 Down-Mix Control Enable. This bit enables JS1 to control the down-mix function (see the JS0DMX description). When this bit is set to 1, JS1 = 1 will activate the down-mix conversion. JS Spread Control Enable. This bit enables 2-channel to 6-channel audio spread function when both jack senses are active (Logic State 1). Note that the SPRD bit can also force the spread function without being gated by the jack senses. See this bit's description in Register 0x76 for more details on the spread function.
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AD1985
Jack Sense Mute Select (JSMT [2:0])
REF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 JS1 OUT OUT IN IN OUT OUT IN IN OUT OUT IN IN OUT OUT IN IN OUT OUT IN IN OUT OUT IN IN OUT OUT IN IN OUT OUT IN IN JS0 OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN JSMT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 JSMT1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 JSMT0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 HP OUT ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE ** ** ** ** ACTIVE ACTIVE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE ** ** ** ** ** ** ** ** LINE OUT ACTIVE ACTIVE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ** ** ** ** FMUTE ACTIVE FMUTE FMUTE FMUTE FMUTE ACTIVE ACTIVE ** ** ** ** ** ** ** ** C/LFE OUT ACTIVE ACTIVE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE ** ** ** ** FMUTE ACTIVE FMUTE FMUTE FMUTE FMUTE ACTIVE ACTIVE ** ** ** ** ** ** ** ** MONO OUT ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE FMUTE FMUTE ** ** ** ** ACTIVE FMUTE FMUTE FMUTE ACTIVE ACTIVE FMUTE FMUTE ** ** ** ** ** ** ** ** NOTES JS0 and JS1 Ignored.
(0) (0) (1) (1) (0) (0) (1) (1) (0) (0) (1) (1) (0) (0) (1) (1) (0) (0) (1) (1) (0) (0) (1) (1) (0) (0) (1) (1) (0) (0) (1) (1)
(0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1)
JS0 No Mute Action, JS1 Mutes Mono and Enables LINE_OUT + C/LFE. Standard 6-Channel Configuration. Swapped HP_OUT and LINE_OUT. JS0 No Mute Action, JS1 Mutes Mono and Enables HP_OUT and C/LFE. Standard 6-Channel Configuration. No Swap. ** Reserved.
JS0 = 0 and JS1 = 0 Enables Mono. JS1 = 1 Enables Front Only. JS0 = 1 and JS1 = 0 Enables All Rear. 6-Channel Configuration with Front Jack Wrap-Back. JS0 No Mute Action, JS1 Mutes Mono and Enables LINE_OUT and HP_OUT and C/LFE. Standard 6-Channel Configuration. Swapped HP_OUT and LINE_OUT. ** Reserved.
** Reserved.
FMUTE = Output is forced to mute independent of the respective volume register setting. ACTIVE = Output is not muted and its status is dependent on the respective volume register setting. OUT = Nothing is plugged into the jack, and therefore, the JS status is 0 (via the load resistor pull-down action). IN = Jack has plug inserted, and therefore, the JS status is 1 (via the codec JS pin internal pull-up). Note: MMDIS (Register 0x70, Bit D7) set to 1 will keep mono out enabled for all the settings above.
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AD1985
Serial Configuration (Index 0x74)
Reg Num 0x74 Name Serial Config. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default SLOT16 REGM2 REGM1 REGM0 REGM3 DRF OMS CHEN SPOVR LBKS1 LBKS0 INTS CSWP SPAL SPDZ SPLNK 0x1001
Note: This register will only reset bits CSWP (D3), LBKS[1:0] (D[6:5]), and OMS (D9) when Register 0x00 is written to (soft reset). All bits are reset on a hard or hardware reset.
SPLNK
SPDZ
SPAL
CSWP
INTS
SPDIF Link. This bit enables the SPDIF to link with the front DACs for data requesting. 0: SPDIF and front DACs are not linked. 1: SPDIF and front DACs are linked and receive same data requests. (Reset default.) SPDIF DACZ. 0: Repeat last sample out the SPDIF stream if FIFO underruns. (Reset default.) 1: Forces midscale sample out the SPDIF stream if FIFO underruns. SPDIF ADC Loop-Around. 0: SPDIF transmitter is connected to the AC Link stream. (Reset default.) 1: SPDIF transmitter is connected to the digital ADC stream, not the AC Link. Swap the Center/LFE Channels. Some systems have a swapped external connection for the center and LFE Channels. Setting this bit will swap these channels internal to the codec. Setting this bit also swaps the definitions of the center/LFE volume controls in Register 0x36. Interrupt Mode Select. This bit selects the audio interrupt implementation path. 0: Slot 12, Bit 0 (modem interrupt) (reset default). 1: Slot 6, Valid Bit (MIC ADC interrupt). Note: This bit does not generate an interrupt. Rather, it steers the path of the generated interrupt. Loop-Back Selection. These bits select the internal digital loop-back path when the LPBK bit is active (see Register 0x20). 00: Loop back through the front DACs. (Reset default.) 01: Loop back through the surround DACs. 11: Loop back through the center and LFE DACs. (Center DAC loops back from the ADC left channel, the LFE DAC from the ADC right channel.) 10: Reserved. SPDIF Override. 0: SPDIF Transmitter is enabled only if the SPDIF pin is pulled low on reset. (Reset default.) 1: SPDIF Transmitter is enabled regardless of the SPDIF pin configuration. Chain Enable. This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45). 0: Disable chaining. (Reset default.) 1: Enable chaining into ID0 pin. Output Microphone Select. This bit will switch the microphone inputs between the MIC1/MIC2 pins and the Center/LFE pins. This feature is used for those systems that have input/output jack sharing. Note: See the charts describing the microphone inputs--the description of MS (Bit D8, Register 0x20) and the record select control register (0x1A). 0: Microphone inputs come from MIC1 and MIC2 pins. Center/LFE outputs behave as expected (default). 1: Microphone inputs now come from the Center/LFE pins. The codec will place the Center/LFE outputs into a High-Z state--equivalent to setting CLDIS (Bit D11, Register 0x76). Setting the OMS bit, however, will not overwrite the CLDIS; Center/LFE outputs respond equally to both bits. DAC Request Force: This allows the AD1985 to synchronize DAC requests with the AD1981A/ AD1981B. 0: Normal DAC requesting sequence. (Reset default.) 1: Synchronize to AD1981A/B DAC requests. Slave 3 Codec Register Mask. Master Codec Register Mask. (Reset default.) Slave 1 Codec Register Mask. Slave 2 Codec Register Mask. Enable 16-Bit Slot Mode. SLOT16 makes all AC Link slots 16 bits in length, formatted into 16 slots. This is a preferred mode for DSP serial port interfacing.
LBKS[1:0]
SPOVR
CHEN
OMS
DRF
REGM3 REGM0 REGM1 REGM2 SLOT16
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AD1985
Miscellaneous Control Bits (Index 0x76)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x76 Misc DACZ AC97NC MSPLT LODIS CLDIS HPSEL DMIX1 DMIX0 SPRD 2CMIC LOSEL SRU VREFH VREFD MBG1 MBG0 0x0000 Control Bits
MBG[1:0]
VREFD, VREFH
SRU
LOSEL
2CMIC
SPRD
MIC Boost Gain Select Register. These two bits allow changing both MIC preamp gain blocks from the nominal +20 dB gain boost. Both MIC1 and MIC2 preamps will be set to the same selected gain. Note: This gain setting only takes effect while Bit D6 (M20) on the MIC volume register (0x0E) is set to 1, otherwise, the MIC boost blocks have a gain of 0 dB. 00: +20 dB gain. (Reset default.) 01: +10 dB gain. 10: +30 dB gain. 11: Reserved. Controls the Level of the VREFOUT Pin as Follows: VREFH VREFD 0 0 2.25 V (Default) 0 1 High-Z 1 0 3.7 V 1 1 0V Sample Rate Unlock. Controls all DAC sample rate locking. 0: All DAC sample rates are locked to the front sample rate. (Reset default.) 1: DAC sample rates can be set independently for front, surround, and LFE. LINE_OUT Amplifiers Input Select. This bit allows the LINE_OUT output amplifiers to be driven by the mixer or the surround DACs. The main purpose for this is to allow swapping of the front and surround channels to make better use of the SURR/HP_OUT output amplifiers. This bit should normally be used in tandem with the HPSEL bit (see below). 0: LINE_OUT amplifiers are driven by the mixer outputs. (Reset default.) 1: LINE_OUT amplifiers are driven by the surround DAC outputs. 2-Channel MIC Select. This bit enables simultaneous recording from MIC1 and MIC2 inputs, using a stereo microphone array. Note that this register works in conjunction with the MS and OMS bits. 0: MIC1 or MIC2 (determined by MS bit) is routed to the mixer/record selector's left and right MIC channels. (Reset default.) 1: MIC1 is routed to the mixer/record selector's left MIC channel, and MIC2 is routed to the mixer/record selector's right MIC channel. The MS bit will swap the MIC1/MIC2 left and right assignments. The OMS bit will select from the MIC1/MIC2 or Center/LFE pins as the input source for the microphone. See the Record Selector (Register 0x1A), MS bit (Bit D8, Register 0x20), or OMS bit (Bit D9, Register 0x74) definitions for more information. Spread Enable. This bit enables spreading of 2-channel media to all six output channels. This function is implemented in the analog section by using the output selector control lines for the center/LFE, surround, and LINE_OUT output channels. Note that the jack sense pins can also be set up to control (gate) this function depending on the JS1SPRD bit (see Register 0x72). 0: No Spreading occurs, unless activated by the jack senses and JS1SPRD bit. (Reset default.) 1: The SPRD selector drives the center and LFE outputs from the MONO_OUT, the HPSEL selector drives the SURR/HP_OUT outputs from the mixer outputs, and the LOSEL selector drives the LINE_OUT outputs from the mixer outputs. Note that the SPRD bit overrides the current output selector control lines, set up by Bits LOSEL and HPSEL as follows: LOSEL = 0 and HPSEL = 1.
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AD1985
DMIX[1:0] Down-Mix Mode Select. Provides analog down-mixing of the center, LFE, and/or surround channels into the mixer channels. This allows the full content of 5.1 or quad media to be played through stereo headphones or speakers. Note that the jack sense pins can also be set up to control (gate) this function depending on the JS0DMX and JS1DMX bits (see Register 0x72). The upper bit allows forcing the down-mix function: DMIX[1] = 0: No down-mix unless activated by the jack senses and JSxDMX bits. (Default.) DMIX[1] = 1: Forces down-mix function. The lower bit selects the down-mix type: DMIX[0] = 0: Selects 6-to-4 down-mix. The center and LFE channels are summed equally into the mixer L/R channels. (Default.) DMIX[0] = 1: Selects 6-to-2 down-mix. The surround L/R channels are summed into the mixer L/R channels. The center and LFE are summed equally into the mixer left and right channels. Default for DMIX[1:0] is 00. Headphone Amplifier Input Select. This bit allows the headphone power amps to be driven from the surround DACs or from the mixer outputs. There are two reasons for this, one is to allow 2-channel media to use the higher power headphone amplifiers available on the SURR/HP_OUT outputs, and the other is to allow spreading of 2-channel media to the surround outputs. Together with the LOSEL bit (see above), this bit also provides for analog swapping of the mixer (front) and surround outputs. 0: SURR_OUT/HP_OUT outputs are driven by the surround DACs. (Reset default.) 1: SURR_OUT/HP_OUT outputs are driven by the mixer outputs. Center and LFE Disable: Disables the center and LFE output pins, placing them into High-Z (approximately 30 k impedance) mode so that the assigned output audio jacks can be shared for MIC inputs or other functions. 0: Center and LFE output pins have normal audio drive capability. (Reset default.) 1: Center and LFE output pins are placed into High-Z mode. LINE_OUT Disable: Disables the LINE_OUT pins (L/R), placing them into High-Z (approximately 30 k impedance) mode so that the assigned output audio jack can be shared for Line Input function. 0: LINE_OUT pins have normal audio drive capability. (Reset default.) 1: LINE_OUT pins are placed into High-Z mode. Mute Split. Allows separate mute control bits for left and right channels in master, HP, LINE_IN, CD, PCM OUT, and record volume/gain control registers. 0: Both left and right channel mutes are controlled by Bit D15 in their respective registers. (Reset default.) 1: Bit D15 affects only the left channel mute and Bit D7 affects only the right channel mute. AC '97 No Compatibility Mode. Changing this bit allows the surround, center, and LFE volume control registers and output attenuators to operate in a more functional mode than what's defined by the AC '97 spec. This is called ADI compatibility mode. In AC '97 compatibility mode, the DAC gain/attenuators for the surround, center, and LFE are controlled by Register 0x18 (PCM volume). The output pin attenuators for the surround are controlled by Register 0x38 and the output pin attenuators for the center and LFE are controlled by Register 0x36. In ADI compatibility mode, the surround DAC gain/attenuators are controlled by Register 0x38 and the center/LFE DAC gain/attenuators are controlled by Register 0x36. The output pin attenuators for the surround, center, and LFE are controlled by Register 0x02 (master volume). 0: AC '97 compatibility mode. (Reset default.) 1: ADI compatibility mode. DAC Zero-Fill. Determines DAC data fill under starved condition. 0: DAC data is repeated when DACs are starved for data. (Reset default.) 1: DAC data is zero-filled when DACs are starved for data.
HPSEL
CLDIS
LODIS
MSPLT
AC97NC
DACZ
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AD1985
Advanced Jack Sense Register (Index 0x78)
Reg Num 0x78 Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default X X X X X X X JS3TMR JS2TMR JS3MD JS2MD JS3ST JS2ST JS3INT JS2INT N/A Advanced X Jack Sense
Note: All register bits are read/write except for JS2ST and JS3ST, which are read-only.
JS2INT
JS3INT JS2ST JS3ST
JS2MD
JS3MD
JS2TMR JS3TMR X
Indicates Pin JS2 Has Generated an Interrupt. Remains set until the software services JS2 interrupt, i.e., JS2 ISR (Interrupt Service Routine) should clear this bit by writing a 0 to it. Notes: 1) Interrupts are generated by valid state changes of JS pins. 2) Interrupt to the system is actually an OR combination of this bit and JS3INT to JS0INT. 3) The interrupt implementation path is selected by the INTS bit (Register 0x74). 4) It is also possible to generate a software system interrupt by writing a 1 to this bit. Indicates Pin JS3 Has Generated an Interrupt. Remains set until the software services the JS3 interrupt, i.e., JS3 ISR (Interrupt Service Routine) should clear this bit by writing a 0 to it. See the JS2INT description above for additional details. JS2 State. This bit always reports the logic state of JS2 pin. Cannot be used for MIC sensing. JS3 State. This bit always reports the logic state of JS3 pin. When the voltage reference is set to 3.7 V, the behavior of this pin is inverted to allow for MIC sensing. In this mode, an inserted jack causes the pin to go low. All other voltage reference levels enable this pin to be used as a standard sense pin. Only JS3 can be used for MIC sensing. JS2 Mode. This bit selects the operation mode for the JS2 pin. 0: Jack Sense Mode. (Reset default.) 1: Interrupt Mode. JS3 Mode. This bit selects the operation mode for the JS3 pin. 0: Jack Sense Mode. (Reset default.) 1: Interrupt Mode. JS2 Timer Enable. If this bit is set to a 1, JS2 must be high for greater than 298 ms to be recognized. JS3 Timer Enable. If this bit is set to a 1, JS3 must be asserted (see JS3ST) for greater than 298 ms to be recognized. Reserved. Do not write.
Vendor ID Registers (Index 0x7C to 0x7E)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x7C Vendor VIDF7 VIDF6 VIDF5 VIDF4 VIDF3 VIDF2 VIDF1 VIDF0 VIDS7 VIDS6 VIDS5 VIDS4 VIDS3 VIDS2 VIDS1 VIDS0 0x4144 ID1
VIDS[7:0]: This register is ASCII encoded to A. VIDF[7:0]: This register is ASCII encoded to D.
Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Num 0x7E Vendor VIDT7 VIDT6 VIDT5 VIDT4 VIDT3 VIDT2 VIDT1 VIDT0 VIDREV7 VIDREV6 VIDREV5 VIDREV4 VIDREV3 VIDREV2 VIDREV1 VIDREV0 0x5375 ID2
VIDT[7:0]: This register is ASCII encoded to S. VIDREV[7:0]: This register is set to 0x75, identifying the AD1985.
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AD1985
Codec Class/Revision Register (Index 0x60, Page 01)
Reg Num 0x60 Name Codec Class/Rev D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default X X X CL4 CL3 CL2 CL1 CL0 RV7 RV6 RV5 RV4 RV3 RV2 RV1 RV0 N/A
New register added for AC '97 2.3.
RV[7:0] CL[4:0] X
Revision ID. (Read-only.) The initial production version of the AD1985 reports three. This will increment with each stepping/revision of the codec chip. Codec Compatibility Class. (Read-only.) The AD1985 will return 0x00 from these bits. Reserved.
PCI Subsystem Vendor ID Register (Index 0x62, Page 01)
Reg Num 0x62 Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default PCI SVID PVI15 PVI14 PVI13 PVI12 PVI11 PVI10 PVI9 PVI8 PVI7 PVI6 PVI5 PVI4 PVI3 PVI2 PVI1 PVI0 N/A
New register added for AC '97 2.3.
PVI[15:0]
PCI Subsystem Vendor ID. (Read/write.) This field provides the PCI subsystem vendor ID of the audio or modem subassembly vendor (i.e., CNR manufacturer, motherboard vendor). This is not the codec vendor PCI vendor ID, nor the AC '97 controller PCI vendor ID. If data is not written by BIOS or other applications, it will return 0xFFFF.
PCI Subsystem Device ID Register (Index 0x64, Page 01)
Reg Num 0x64 Name PCI SID D15 PI15 D14 PI14 D13 PI13 D12 PI12 D11 PI11 D10 PI10 D9 PI9 D8 PI8 D7 PI7 D6 PI6 D5 PI5 D4 PI4 D3 PI3 D2 PI2 D1 PI1 D0 PI0 Default N/A
New register added for AC '97 2.3.
PI[15:0]
PCI Vendor ID. (Read/write.) This field provides the PCI subsystem ID of the audio or modem subassembly (i.e., CNR model, motherboard SKU). This is not the codec vendor PCI ID, nor the AC '97 controller PCI ID. Information in this field must be available for AC '97 controller reads when codec ready is asserted in AC link. If data is not written by BIOS or other applications, it will return 0xFFFF.
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AD1985
Function Select Register (Index 0x66, Page 01)
Reg Num 0x66 Name Function Select D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default X X X X X X X X X X X FC3 FC2 FC1 FC0 T/R 0x0000
New register added for AC '97 2.3.
FC[3:0]
T/R
Function Code Bits. (Default 0.) These bits specify the type of audio function described by this page. 0x00: DAC 1 (Master Out). Maps to line out L/R, codec Pins 35 and 36. 0x01: DAC 2 (AUX Out). Maps to surround/HP out L/R, codec Pins 39 and 41. 0x02: DAC 3 (Center/LFE). Maps to center/LFE, codec Pins 31 and 32. 0x03: S/P-DIF Out. 0x04: Phone In. 0x05: Mic 1 (Mic Select = 0). 0x06: Mic 2 (Mic Select = 1). 0x07: Line In. 0x08: CD In. 0x09: Video In. 0x0A: Aux In. 0x0B: Mono Out 0x0C to 0x0F: Reserved. These bits are read/write and represent current AC '97 2.3 defined I/O capabilities. Software will program the corresponding I/O number in this field together with the tip/ring selector bit T/R. Once software programs the value and properly reads it back to confirm selection and implementation, it will access the rest of the bit fields in the descriptor. A read-only value of 0 in this register, along with a read-only value of 0 in the IV (Register 0x68 page 01) bit, indicates the codec does not support the information and I/O register. Tip or Ring Selection Bit. (Default is 0.) This bit sets which jack conductor the sense value is measured from. Software will program the corresponding ring/tip selector bit together with the I/O number in Bits FC[3:0]. Once software programs the value and properly reads it back to confirm selection and implementation, it will access the rest of the bit fields in the descriptor. 0: Tip 1: Ring Mono inputs and outputs report the relevant function and sense information when T/R is set to 0 (tip).
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AD1985
Information and I/O Register (Index 0x68, Page 01)
Reg Num 0x68 Name Function Information D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default G4 G3 G21 G1 G0 INV DL4 DL3 DL2 DL1 DL0 IV X X X FIP N/A
New register added for AC '97 2.3. Data read back from this register is invalid unless a function is first specified in Register 0x66, page 01.
G[4:0]
INV
DL[4:0]
IV
FIP
Gain Bits. (Read/write.) The codec updates these bits with the gain value (dB relative to level out) in 1.5 dBV increments, not including the volume control gains. For example, if the volume gain is 0 dB, then the output pin should be 0 dB level. Any difference is the gain reflected here. When relevant, the BIOS further updates these bits to take into consideration external amplifiers or other external logic that it knows about. G[3:0] indicates the magnitude of the gain. G[4] indicates whether the value is a gain or attenuation--essentially a sign bit. G[4:0] Gain or Attenuation (dB Relative to Level Out) 0 0000 0 dBV 0 0001 1.5 dBV 0 1111 24 dBV 1 0001 -1.5 dBV 1 1111 -24 dBV Inversion Bit. (Read/write.) Indicates that the codec presents a 180 phase shift to the signal. 0: No inversion reported. 1: Inverted. Buffer Delays (read/write) The default value is the delay internal to the codec. The BIOS may add to this value the known delays external to the codec, such as for an external amplifier, logic, etc. The codec provides a number representing a delay measurement for the input and output channels. Software will use this value to accurately calculate the audio stream position with respect to what has been reproduced or recorded. These values are in 20.83 s (1/48000 second) units. For output channels, this timing is from the end of the AC link frame in which the sample is provided, until the time the analog signal appears at the output pin. For input streams, this is from when the analog signal is presented at the pin until the representative sample is provided on the AC link. Analog-to-analog paths are not considered in this measurement. The measurement is a typical measurement, at a 48 kHz sample rate, with minimal in-codec processing. 0x00: Information not provided. 0x01 to 0x1E: Buffer delay in 20.83 s units. 0x1F: Reserved. Information Valid Bit. Indicates whether a sensing method is provided by the codec and if information field is valid. This field is updated by the codec. 0: (A) After codec reset de-assertion, it indicates the codec does not provide sensing logic and this bit will be read-only. (B) After a sense cycle is completed, indicates that no information is provided on the sensing method. 1: (A) After codec reset de-assertion, it indicates the codec provides sensing logic for this I/O and this bit is read/write. (B) After clearing this bit by writing 1, when a sense cycle is completed, indicates that there is valid information in the remaining descriptor bits. Writing 0 to this bit has no effect. Function Information Present. (Read-only.) 1: The G[4:0], INV, and DL[4:0] (in Register 0x68) bits and the ST[2:0] (in Register 0x6A) bits are supported and are read/write capable. 0: The G[4:0], INV, DL[4:0], and ST[2:0] bits are not supported and are read-only with a value of 0.
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AD1985
Sense Register (Index 0x6A, Page 01)
Reg Num 0x6A Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Sense Register ST2 ST1 ST0 S4 S3 S2 S1 S0 OR1 OR0 SR5 SR4 SR3 SR2 SR1 SR0 N/A
New register added for AC '97 2.3.
ST[2:0]
S[4:0]
Connector/Jack Location Bits. (Read/write.) This field describes the location of the jack in the system. This field is updated by the BIOS. 0x0: Rear I/O Panel. 0x1: Front Panel. 0x2: Motherboard. 0x3: Dock/External. 0x4 to 0x6: Reserved. 0x7: No Connection/Unused I/O. Sensed Bits Relate to the I/O Being Sensed as Input or Output. (Read-only.) Sensed Bits (When Output Sense Cycle Initiated). This field allows for the reporting of the type of output peripheral/device plugged in the jack. Values specified below should be interrogated with the SR[5:0] and OR[1:0] for accurate reporting. 0x00: Data Not Valid. Indicates that the reported value(s) is invalid. 0x01: No Connection. Indicates that there are no connected devices. Default. 0x02: Fingerprint. Indicates a specific fingerprint value for devices that are not specified or are unknown. 0x03: Speakers (8 ). 0x04: Speakers (4 ). 0x05: Powered Speakers. 0x06: Stereo Headphone. 0x07: SPDIF Out (Electrical). 0x08: SPDIF Out (TOS). 0x09: Mono Headset. (Mono speaker left channel and MIC. Read Functions 5 and 6 for matching microphone.) (Not supported.) 0x0A: Other. Allows a vendor to report sensing other type of devices/peripherals. SR[5:0] together with OR[1:0] provide information regarding the type of device sensed. 0x0B to 0x0E: Reserved. 0x0F: Unknown (Use Fingerprint). Sensed Bits (When Input Sense Cycle Initiated) This field allows for the reporting of the type of input peripheral/device plugged in the jack. Values specified below should be interrogated with the SR[5:0] and OR[1:0] bits for accurate reporting. 0x10: Data Not Valid. Indicates that the reported value(s) is invalid. 0x11: No Connection. Indicates that there are no connected devices. Default. 0x12: Fingerprint. Indicates a specific fingerprint value for devices that are not specified. 0x13: Microphone (Mono). 0x14: Stereo Microphone. 0x15: Stereo Line In (CE Device Attached). 0x16: Mono Line In (CE Device Attached) . 0x17: SPDIF In (Electrical). 0x18: SPDIF In (TOS). 0x19: Headset. (Mono speaker left channel and MIC. Read Functions 0 to 3 for matching DAC out.) 0x1A: Other. Allows a vendor to report sensing other types of devices/peripherals. SR[5:0] together with OR[1:0] provide information regarding the type of device sensed. 0x1B to 0x1E: Reserved. 0x1F: Unknown (Use Fingerprint).
Rev. A | Page 45 of 48
AD1985
OR[1:0] Order Bits. These bits indicate the order of magnitude that the sense result Bits SR[5:0] are using. Default is 0x0. 00: 100 01: 101 10: 102 11: 103 For example, SR = 1, OR = 11; if measuring resistance, result is 1 k. Sense Result Bits. (Read-only, default 0.) These bits are used to report a vendor specific fingerprint or value. (Resistance, impedance, reactance, etc.)
SR[5:0]
Codec ID and Clock Selection
XTL_IN GND GND GND XTAL CLK Input CLK Input CLK Input ID1 0 0 1 1 0 0 1 ID0 0 1 0 1 0 1 X CODEC ID Secondary, ID = 3 Secondary, ID = 2 Secondary, ID = 1 Primary, ID = 0 Primary, ID = 0 Primary, ID = 0 Reserved CODEC CLOCKING SOURCE 12.288 MHz (BIT_CLK from Primary Codec) 12.288 MHz (BIT_CLK from Primary Codec) 12.288 MHz (BIT_CLK from Primary Codec) 24.576 MHz (Local XTAL or External CLK into XTL_IN) 14.31818 MHZ (External into XTL_IN) 48.000 MHZ (External into XTL_IN) Reserved
Note that internally, the ID pins have weak pull-ups and are inverted. Note also that the clock detection is done per AC '97 Rev. 2.3 specification.
Rev. A | Page 46 of 48
AD1985 OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
48 1
9.00 BSC SQ
37 36
PIN 1
1.45 1.40 1.35
10 6 2
SEATING PLANE
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
TOP VIEW
(PINS DOWN)
7.00 BSC SQ
VIEW A
12 13 24 25
0.15 0.05
SEATING PLANE
0.50 BSC
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
0.27 0.22 0.17
Figure 12. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters
ORDERING GUIDE
Model AD1985JST AD1985JST-REEL AD1985JSTZ1 AD1985JSTZ-REEL1 Temperature Range 0C to +70C 0C to +70C 0C to +70C 0C to +70C Package Description 48-Lead LQFP 48-Lead LQFP 48-Lead LQFP 48-Lead LQFP Package Option ST-48 ST-48 ST-48 ST-48
1
Z = Pb-free part.
Rev. A | Page 47 of 48
AD1985 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03610-0-3/04(A)
Rev. A | Page 48 of 48

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